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| [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 1 - 1. g eneral d escription the ak 7755 is a highly integrated digital signal processor, including a mono adc, a stereo audio codec , a mic pre - amplifier , a line - out amplifier and digital a udio i/f. the audio dsp has 2560 step at fs = 48 khz parallel pro cessing power. as the ak 7755 is a ram based dsp, it is programmable for user requirements such as high performance hands free function and acoustic effect s . the ak 7755 is avai lable in a space saving small 3 6 - pin qfn package. 2. f eatures ? dsp - word length: 24 - bit (data ram 24 - bit floating point) - instruction cycle: 8.1ns (2560fs at fs=48 khz) - multiplier 2 4 x 2 4 4 8 - bit (double precision available) - divider 20 / 20 20 - bit ( with floating point normalization function) - alu: 52 - bit ar ithmetic operation (with overflow margin 4 - bit) - program ram: 4096 36 - bit - coefficient ram: 2048 24 - bit - data ram: 2048 24 - bit (24 - bit floating point) - offset register: 32 13 - bit - delay ram : 8 192 24 - bit - acc elerator coefficient ram: 2048 20 - bit - accelerator data ram: 2048 16 - bit - jx pins (interrupt) - master/slave operation - master clock : 2560 fs (internally generated by pll from 32, 48, 64, 128, 256 and 384fs clock) ? two digital interfaces ( i/f 1, i/f2) - digital signal input port (4ch): msb justified 24 - bit, lsb justified 24/ 20 / 16 - bit , i 2 s - digital signal input port (6ch): msb justified 24 - bit, lsb justified 24/20/16 - bit, i 2 s - short / long frame - 24 - bit linear , 8 - bit a - law, 8 - bit - law - tdm 2 56 fs (8ch) msb justified and i 2 s formats ? stereo 24 - bit adc: - sampling frequency: fs= 8khz ~ 96k hz - adc characteristics s/(n+d): 9 1 db, dr, s/n: 102 db - two - channel analog input selector (differential, single - ended input) - channel independent mic analog gain amplifier (0~18db ( 2 db step), 18~ 36 db ( 3 db step)) - analog drc (dynamic range control) - channel independent digital volume (24~ - 103db, 0.5db step mute) - digital hpf for dc offset cancelling ? mono 24 - bit adc - sampl ing frequency: 8khz ~ 96khz - adc characteristics s/(n+d): 90 db ; dr, s/n: 100 db - line amplifier: 21 db ~ - 21db, 3db step - digital volume (24db ~ - 103db, 0.5 db step, mute) - digital hpf for dc offset cancelling dsp with mono adc stereo codec + mic/lineout amp ak 775 5
[ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 2 - ? stereo 24 - bit dac - sampling frequency: fs =8khz ~ 96khz - digital volume (12db ~ - 115db, 0.5step, mute) - digital de - emphasis filter (tc=50/15us, fs=32khz, 44.1khz, 48khz) ? line output - single - ended output - s/(n+d): 91 db, dr, s/n: 106db - stereo analog volume (+0db ~ - 28 db , 2.0 db step , mute ) ? analog mixer ? digital mixer ? 4ch digital microphone interface ? i 2 c bootloader - eeprom mat selectable ? p interface : spi, i 2 c - bus (400khz fast mode) ? power supply a nalog (avdd) : 3.0v ~ 3.6v (typ. 3.3v) digital1 (dvdd): 1.1 4 v ~ 1.3v (typ. 1.2 v) (e xternal power supply or internal regulator is selectable) i/f (tvdd) : 1.7v ~ 3.6v (typ. 3.3 v) ? operating t emperature r ange: - 4 0 ? ? ? package: 3 6 - pin qfn (0.5mm pitch ) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 3 - 3. table of contents 1. general description ................................ ................................ ................................ ................................ ................. 1 2. features ................................ ................................ ................................ ................................ ................................ .... 1 3. table of contents ................................ ................................ ................................ ................................ ..................... 3 4. block diagram and functions ................................ ................................ ................................ ................................ . 4 block diagram ................................ ................................ ................................ ................................ .......... 4 dsp block diagram ................................ ................................ ................................ ................................ .. 5 5. pin configurations and functions ................................ ................................ ................................ ........................... 6 ordering guide ................................ ................................ ................................ ................................ .......... 6 pin layout ................................ ................................ ................................ ................................ ................. 6 pin functions ................................ ................................ ................................ ................................ ............. 9 handling of unused pin ................................ ................................ ................................ .......................... 10 6. absolute maximum ratings ................................ ................................ ................................ ................................ .. 11 7. recommended operating conditions ................................ ................................ ................................ .................... 11 8. electrical characteristics ................................ ................................ ................................ ................................ ....... 12 analog characteristics ................................ ................................ ................................ ............................ 12 dc characteristics ................................ ................................ ................................ ................................ ... 17 power consumptions ................................ ................................ ................................ ............................... 17 digital filter characteritics ................................ ................................ ................................ ..................... 18 switching characteristics ................................ ................................ ................................ ........................ 19 9. functional description ................................ ................................ ................................ ................................ .......... 26 system clock ................................ ................................ ................................ ................................ ........... 26 control register settings ................................ ................................ ................................ ......................... 30 power - up sequence ................................ ................................ ................................ ................................ . 52 ldo (internal circuit drive r egulator) ................................ ................................ ................................ .. 55 power - down sequence ................................ ................................ ................................ ............................ 55 power - down and reset ................................ ................................ ................................ ............................ 56 ram clear ................................ ................................ ................................ ................................ .............. 58 serial data interface ................................ ................................ ................................ ................................ 59 p interface setting and pin status ................................ ................................ ................................ ......... 66 spi interface (i2csel pin = l) ................................ ................................ ................................ ........... 66 i 2 c bus interface (i2csel pin= h) ................................ ................................ ................................ ..... 79 analog input block ................................ ................................ ................................ ................................ . 84 adc block ................................ ................................ ................................ ................................ .............. 87 dac blocks ................................ ................................ ................................ ................................ ............ 90 analog output block ................................ ................................ ................................ ............................... 92 simple write error check ................................ ................................ ................................ ....................... 94 eeprom interface ................................ ................................ ................................ ................................ .. 95 digital microphone interface ................................ ................................ ................................ .................. 99 digital mixer ................................ ................................ ................................ ................................ ......... 100 10. recommended external circuits ................................ ................................ ................................ ....................... 101 connection diagram ................................ ................................ ................................ .............................. 101 periphe ral circuit ................................ ................................ ................................ ................................ .. 105 11. package ................................ ................................ ................................ ................................ .............................. 107 outline dimensions ................................ ................................ ................................ ............................... 107 package & lead frame material ................................ ................................ ................................ ............ 107 marking ................................ ................................ ................................ ................................ ................. 108 12. revision history ................................ ................................ ................................ ................................ ................ 109 important notice ................................ ................................ ................................ ................................ ........ 109 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 4 - 4. block diagram and functions block diagram figure 1 . block diagram [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 5 - dsp block d iagram figure 2 . dsp block diagram t mp 8 28bit sdout3 cp0, cp1 dp0, dp1 d ata ram 2048 w x 24 - bit (20.4f) mpx 2 4 mpx 24 x y multiply 2 4 2 4 4 8 - bit micon i/f control pram 4096 w 36 - bit dec pc stack : 5level (max) mul dbus shift a b alu 52 - b it overflow margin: 4 - bit dr0 ? 3 over flow data generator division 20 ? 20 20 peak detector serial i/f cbus ( 2 4 - bit) dbus( 2 8 - bit) 48 - bit 2 8 - bit 4 8 - bi t 52 - bit 52 - b it 8192 w x 2 4 - bit ( 20 .4f) p tmp (lifo) 6 2 4 - bit d l p0, d l p1 din 1 2 16 / 20/ 24 - bit 2 16 / 20/ 24 - bit 52 - b it dout1 tmp 12 24 - bit 2 1 6 / 20/ 24 - bit dout2 dout3 2 16 / 20/ 24 - bit 2 16 / 20/ 24 - bit din 3 din 2 2 16 / 20/ 24 - b it accelerator coefficient ram ( ac c ram ) 2048 w x 20 - bit data ram ( a c dram ) 2048 w x 1 6 - bit ofr eg 32w x 1 3 - bit 2 16/ 20/ 24 - bit dout4 2 16 / 20/ 24 - bit din 4 d e lay ram coefficient ram 2048 w 2 4 - bit pointer [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 6 - 5. pin configurations and functions ordering guide ak 7755 en/vn - 4 0 ? +85 ? c 3 6 - pin qfn (0.5mm pitch) akd 7755 evaluation board for ak 7755 pin layout figure 3 . pin layout 9 clko input out put i/o power pin 1 2 3 4 5 6 7 8 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 2 6 2 5 2 4 2 3 22 21 20 3 6 3 5 3 4 33 32 31 30 2 9 vcom i2csel sdin2/jx 1 sdin1/jx0 sto /rdy lrck bick xti tvdd dvss sdout3 / jx2 / mat 1 s dout 2 / jx3 / mat0 s dout1/eest csn / cad /matsel ldoe dvss dvdd / avdrv avdd pdn out 2 avdd avss avdd in4/inn 2 /dmclk2 in3/inp2 /dmdat2 in2/inn1 /dmclk1 3 6 pin qfn (top view) xto avss out 3 in1/inp1 /dmdat1 lin 18 s clk / scl 19 si/exteep 28 out1 s o /s da [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 7 - i2csel pin = l i2csel pin = h, exteep pin = l 9 clko input out put i/o power pin 1 2 3 4 5 6 7 8 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 2 6 2 5 2 4 2 3 22 21 20 3 6 3 5 3 4 33 32 31 30 2 9 vcom i2csel = l sdin2/jx 1 sdin1/jx0 sto /rdy lrck bick xti tvdd dvss sdout3 / jx2 s dout 2 / jx3 s dout1 /eest csn ldoe dvss dvdd / avdrv avdd pdn out 2 avdd avss avdd in4/inn2 /dmclk2 in3/inp2 /dmdat2 in2/inn1 /dmclk1 3 6 pin qfn (top view) xto avss out 3 in1/inp1 /dmdat1 lin 18 s clk 19 s i 28 out1 s o 9 clko input out put i/o power pin 1 2 3 4 5 6 7 8 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 2 6 2 5 2 4 2 3 22 21 20 3 6 3 5 3 4 33 32 31 30 2 9 vcom i2csel = h sdin2/jx 1 sdin1/jx0 sto /rd y lrck bick xti tvdd dvss sdout3 / jx2 s dout 2 / jx3 s dou t1/eest c ad ldoe dvss dvdd / avdrv avdd pdn out 2 avdd avss avdd in4/inn2 /dmclk2 in3/inp 2 /dmdat2 in2/inn1 /dmclk1 3 6 pin qfn (top view) xto avss out 3 in1/inp 1 /dmdat1 lin 18 scl 19 exteep= l 28 out1 s da [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 8 - i2csel pin = h, exteep pin = h, matsel pin = l i2csel pin = h, exteep pin = h, matsel pin = h 9 clko input out put i/o power pin 1 2 3 4 5 6 7 8 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 2 6 2 5 2 4 2 3 22 21 20 3 6 3 5 3 4 33 32 31 30 2 9 vcom i2csel = h sdin2/jx 1 sdin1/jx0 sto /r dy lrck bick xti tvdd d vss sdout3 / jx2 s dout 2 / jx3 s dout1/eest matsel= l ldoe dvss dvdd / avdrv avdd pdn out 2 avdd avss avdd in4/inn2 /dmclk2 in3/inp2 /dmdat2 in2/inn 1 /dmclk1 3 6 pin qfn (top view) xto avss out 3 in1/inp1 /dmdat1 lin 18 scl 19 exteep= h 28 out1 s da 9 clko input out put i/o power pin 1 2 3 4 5 6 7 8 10 1 1 1 2 1 3 1 4 1 5 1 6 1 7 2 7 2 6 2 5 2 4 2 3 22 21 20 3 6 3 5 3 4 33 32 31 30 2 9 vcom i2csel = h sdin2/jx 1 sdin1/jx0 sto /rdy lrck bick xti tvdd dvss mat1 mat0 s dout1/ee st matsel= h ldoe dvss dvdd / avdrv avdd pdn out 2 avdd avss avdd in4/inn 2 /dmclk2 in3/inp 2 /dmdat2 in2/inn1 /dmclk1 3 6 pin qfn (top view) xto avss out 3 in1/inp1 /dmdat1 lin 18 scl 19 exteep= h 28 out1 s da [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 9 - pin functions no . pin name i/o function 1 vcom o common voltage output pin of analog block ? 2.2f ? 2 avss - analog ground pin 0v 3 i2csel i i 2 c - bus select pin ? l: ? h: 2 c - bus interface the i2csel pin must be fixed to l (dvss) h (tvdd) 4 sdin2 i serial data input 2 pin jx 1 i external conditional jump1 pin (jx1e bit = 5 sdin1 i serial data input1 pin jx 0 i external conditional jump 0 pin (jx0e bit = 6 sto o status output pin rdy o rdy pin 7 lrck i/o lr channel select p in ( internal pull - down ) 8 bick i/o serial bit clock output pin ( internal pull - down ) 9 clko o clock output pin 10 xto o crystal oscillator o utput pin ? ? 11 xti i crystal oscillator input pin ? ? 12 t vdd - digital io power s u pply pin : 1.7 ~ 3.6v (typ. 3.3v) 13 dvss i ground pin 0v 14 sdout3 o serial data output3 pin jx2 i external conditional jump2 pin (jx2e bit = mat1 i i2csel pin = exteep pin = matsel pin = 15 sdout2 o serial data output2 pin jx3 i external conditional jump3 pin (jx3e bit = mat0 i i2csel pin = exteep pin = matsel pin = 16 sdout1 o serial data output1 pin eest o eeprom interface status 17 so o so pin ( i2csel pin = l sda i/o i 2 cbus interface ( i2csel pin = h 18 sclk i serial data clock pin for spi interface ( i2csel pin = l ? scl i/o i 2 cbus interface pin ( i2csel pin = h 19 si i serial data input pin for spi interface ( i2csel pin = l ? exteep i eeprom download control pin ( i2csel pin = h [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 10 - 20 cs n i chipselectn pin for spi interface ( i2csel pin = l ? cad i i2cbus address pin ( i2csel pin = h matsel i eeprom mat select pin ( i2csel pin = exteep pin = 21 a vdd - analog power supply pin : (typ . 3.3 v) 22 pd n i power - down n pin ? ? 23 ldoe i ldo select pin ldoe pin = : : l(dvss) vdd) 24 dvdd i power supply pin for digital core: (typ. 1.2v) avdrv o ldo output (ldoe pin = 25 dvss - ground pin 0v 2 6 out 2 o line output 2 pin 2 7 out 3 o line output 3 pin 2 8 out1 o line output 1 pin 29 avdd - analog p ower supply pin : 3.3v (typ) 30 avss - analog ground pin 0v 31 in4/inn2 i adc input pin (aine bit = 32 in3/inp2 i adc input pin (aine bit = 33 in2/inn1 i adc input pin (aine bit = 34 in1/inp1 i adc input pin (aine bit = 35 lin i mono adc input pin 36 avdd - analog power supply pin : 3.3v (typ) note 1 . all digital input pins must not be allowed to float . if analog input pins are not used, leave them open. the i2csel pin , ldoe pin and cad/matsel pin should be fixed to l ( dv s s) or h ( t vdd). handling of unused pin the unused i/o pins must be processed appropriately as below. classification pin name setting analog lin, in1/inp1 /dmdat1 , in2/inn1 /dmclk1 , in3/inp2 /dmdat2 , in4/inn2 /dmclk2, out1, out2, out3 these pins must be open. digital sto/ rdy, clko, xti, xto, sdout3 / jx2/ mat1 , sdout2 / jx3/ mat0 , sdout1 /eest , so/sda , lrck, bick th ese pin s must be open. i2csel, sdin2/jx1, sdin1/jx0, sclk/scl, si/exteep, csn/cad / matsel, ldoe th ese pin s must be connected to dvss . [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 11 - 6. a bsolute m aximum r atings ( avss=dvss=0v ; note 2 ) parameter symbol min max unit power supplies analog digita l1(i/f) digital 2(core) dvss - avss ( note 2 ) avdd tvdd dvdd gnd 7. r ecommended o perating c onditions ( a vss= d vss =0v; note 2 ) parameter symbol min typ max unit power supplies analog di gita l1(i/f) digital 2(core) avdd tvdd dvdd 3.0 1.7 1.1 4 3.3 3.3 1.2 3.6 3.6 1.3 v v v note 5 . avdd and tvdd must be powered up first before dvdd when dvdd is suppl ied externally (ldoe pin = l ). in this case, the power - up se quence between avdd and tvdd is not critical. when using the internal regulator (ldoe pin = h ), t he p ower - up sequence bet ween avdd and t vdd is not critical. but all power supplies must be on before start ing operation of the ak 7755 by pdn pin = h . note 6 . do not turn off the power supply of the ak77 55 with the power supply of the surrounding device turned on. pull - up of sda and scl pins must not exceed t vdd. * akm assumes no responsibility for the usage beyond the condi tions in this datasheet. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 12 - 8. electrical characteristics v analog characteristics 1. mic amplifier gain ( ta= 25 q c ; avdd=tvdd=3.3v; dvdd=1.2v; avss=dvss=0v ) parameter min typ max unit mic amp input impedance 14 20 n gain mgnl[3:0]bits=0h, mgnr[3:0]bits=0h 0 db mgnl[3:0]bits=1h, mgnr[3:0]bits=1h 2 db mgnl[3:0]bits=2h, mgnr[3:0]bits=2h 4 db mgnl[3:0]bits=3h, mgnr[3:0]bits=3h 6 db mgnl[3:0]bits=4h, mgnr[3:0]bits=4h 8 db mgnl[3:0]bits=5h, mgnr[3:0]bits=5h 10 db mgnl[3:0]bits=6h, mgnr[3:0]bits=6h 12 db mgnl[3:0]bits=7h, mgnr[3:0 ]bits=7h 14 db mgnl[3:0]bits=8h, mgnr[3:0]bits=8h 16 db mgnl[3:0]bits=9h, mgnr[3:0]bits=9h 18 db mgnl[3:0]bits=ah, mgnr[3:0]bits=ah 21 db mgnl[3:0]bits=bh, mgnr[3:0]bits=bh 24 db mgnl[3:0]bits=ch, mgnr[3:0]bits=ch 27 db mgnl[3 :0]bits=dh, mgnr[3:0]bits=dh 3 0 db mgnl[3:0]bits=eh, mgnr[3:0]bits=eh 33 db mgnl[3:0]bits=fh, mgnr[3:0]bits=fh 36 db 2. line - in amplifier gain ( ta= 25 q c ; avdd=tvdd=3.3v; dvdd=1.2v; avss=dvss=0v ) parameter min typ max unit line - in amp input im pedance 14 20 n gain ( note 7 ) lign[3:0]bits=0h 0 db lign[3:0]bits=1h - 3 db lign[3:0]bits=2h - 6 db lign[3:0]bits=3h - 9 db lign[3:0]bits=4h - 12 db lign[3:0]bits=5h - 15 db lign[3:0]bits=6h - 18 db lign[3:0]bits=7h - 21 db lign[3:0]bits= 8 h n/a db lign[3:0]bits=9h +3 db lign[3:0]bits=ah +6 db lign[3:0]bits=bh +9 db lign[3:0]bits=ch +12 db lign[3:0]bits= d h + 15 db lign[3:0]bits= e h + 18 db lign[3:0]bits= f h + 21 d b note 7 . if the output signal of line - in amplifier is input to the analog mixer, +18db gain is added to the signal at the mixer. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 13 - 3. mic amp + adc ta= 25 ? c ; avdd=tvdd=3.3v; dvdd=1.2v; avss=dvss=0v; signal frequency 1khz; sampling r ate fs=48khz; measurement frequency =20hz to 20khz sampling rate fs= 96 khz; measurement frequency =20hz to 4 0khz ckm mode0(ckm[2:0]= 000 ); bitfs[1:0]= 00 (64fs); differential input mode note 8 . s/(n+d) when - 60db fs signal is applied. note 9 . indicates i nter - channe l isolation between lch and rch w hen C 1dbfs si g nal is input. note 10 . inp1/inn1 and inp2/inn2 pins. note 11 . in1 , in 2 , in 3 and in 4 pins. note 12 . mgnl/r[3:0] bits = 0h (0db) note 13 . mgnl/r[3:0] bits = 9 h ( 18 db) parameter min typ max unit mic amp + adc resolution 24 bit d ynamic characteristics ( differential input mode ) s/(n+d) ( - 1dbfs) f s=48khz ( note 12 ) 80 9 1 db f s=48khz ( note 13 ) 8 8 f s=96khz ( note 12 ) 8 9 f s=96khz ( note 13 ) 85 dynamic range ( note 8 ) f s=48khz (a - weighted) ( note 12 ) 94 102 db f s=48k hz (a - weighted) ( note 13 ) 9 3 f s=96khz ( note 12 ) 95 f s=96khz ( note 13 ) 89 s/n f s=48khz (a - weighted) ( note 12 ) 94 102 db f s=48khz (a - weighted) ( note 13 ) 93 f s=96khz ( note 12 ) 95 f s=96khz ( note 13 ) 89 inter - channel isolation ( note 9 ) 90 105 db dc accuracy ( differential input ) channel gain mismatch 0.0 0.3 db analog input input voltage ( differential input ) ( note 10 ) ( note 12 ) 2.0 2.2 2.4 vp - p ( note 13 ) 0. 2 77 input voltage ( single - ended input ) ( note 11 ) ( note 12 ) 2.0 2.2 2.4 vp - p ( note 13 ) 0. 2 77 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 14 - 4. line - in amp + adc ta = 25 ? c ; avdd=tvdd=3.3v; dvdd=1.2v; avss=dvss=0v ; signal frequency 1kh z; sampling rate fs=48khz; measurement frequency =20hz to 20khz sampling rate fs= 96 khz; measurement frequency =20hz t o 4 0khz ckm mode0(ckm[2:0]= 000 ); bitfs[1:0]= 00 (64fs); note 14 . s/(n+d) when - 60db fs signal is applied. note 15 . the lin pin. note 16 . li gn[3:0] bits = 0h (0db) note 17 . lign [3:0] bits = e h (+ 1 8 db) parameter min typ max unit line - in amp + adc resolution 24 bit dynamic characteristics s/(n+d) ( - 1dbfs) f s=48khz ( note 16 ) 77 90 db f s=48kh z ( note 17 ) 86 f s=96khz ( note 16 ) 88 f s=96khz ( note 17 ) 85 dynamic range ( note 14 ) f s=48khz (a - weighted) ( note 16 ) 92 100 db f s=48khz (a - weighted) ( note 17 ) 90 f s=96khz ( note 16 ) 95 f s=96khz ( note 17 ) 86 s/n f s=48khz (a - weighted) ( note 16 ) 92 100 db f s=48khz (a - weighted) ( note 17 ) 90 f s=96khz ( note 16 ) 95 f s=96khz ( note 17 ) 86 analog input input voltage ( note 15 ) ( note 16 ) 2.00 2.20 2.40 vp - p ( note 17 ) 0.277 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 15 - 5. line - out amp gain ta= 25 ? c ; avdd= t vdd=3.3v; dvdd=1. 2 v; avss=dvss=0v parameter min typ max unit line - out amp gain lovol1[ 3 :0]bits=0h , lovol2[ 3 :0]bits=0h , lovol 3 [ 3 :0]bits=0h mute d b lovol1[ 3 :0]bits=1h , lovol2[ 3 :0]bits=1h , lovol 3 [ 3 :0]bits= 1 h - 28 db lovol1[ 3 :0]bits=2h , lovol2[ 3 :0]bits=2h , lovol 3 [ 3 :0]bits= 2 h - 26 db lovol1[ 3 :0]bits=3h , lovol2[ 3 :0]bits=3h , lovol 3 [ 3 :0]bits= 3 h - 24 db lovol1[ 3 :0]bits=4h , lovol2[ 3 :0]bits=4h , lovol 3 [ 3 :0]bits= 4 h - 22 db lovol1[ 3 :0]bits=5h , lovol2[ 3 :0]bits=5h , lovol 3 [ 3 :0]bits= 5 h - 20 db lovol1[ 3 :0]bits=6h , lovol2[ 3 :0]bits=6h , lovol 3 [ 3 :0]bits= 6 h - 18 db lovol1[ 3 :0]bits=7h , lovol2[ 3 :0]bits=7h , lovol 3 [ 3 :0]bits= 7 h - 16 db lovol1[ 3 :0 ]bits= 8 h , lovol2[ 3 :0]bits= 8 h , lovol 3 [ 3 :0]bits= 8 h - 14 db lovol1[ 3 :0]bits= 9 h , lovol2[ 3 :0]bits= 9 h , lovol 3 [ 3 :0]bits= 9 h - 12 db lovol1[ 3 :0]bits= a h , lovol2[ 3 :0]bits= a h , lovol 3 [ 3 :0]bits= a h - 10 db lovol1[ 3 :0]bits= b h , lovol2[ 3 :0]bits= b h , lovol 3 [ 3 :0]bi ts= b h - 8 db lovol1[ 3 :0]bits= c h , lovol2[ 3 :0]bits= c h , lovol 3 [ 3 :0]bits= c h - 6 db lovol1[ 3 :0]bits= d h , lovol2[ 3 :0]bits= d h , lovol 3 [ 3 :0]bits= d h - 4 db lovol1[ 3 :0]bits= e h , lovol2[ 3 :0]bits= e h , lovol 3 [ 3 :0]bits= e h - 2 db lovol1[ 3 :0]bits= f h , lovol2[ 3 : 0]bits= f h , lovol 3 [ 3 :0]bits= f h 0 db [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 16 - 6. dac+line - out amp t a= 25 ? c ; avdd=tvdd=3.3v; dvdd=1.2v; avss=dvss=0v; signal frequency 1khz; sampling rate fs=48khz; measurement frequency =20hz to 20khz sampling rate fs= 96 khz; measurement frequency =20hz to 4 0khz ck m mode0(ckm[2:0]=000); bitfs[1:0] bits = 00; lovol1/2/3[3:0] bits = fh(0db); parameter min t yp max unit dac resolution 24 bit dynamic characteristics 1 ( out1, out2, out3 ) s/(n+d) (0 dbfs) fs=48khz 80 91 db fs= 96 khz 89 dynamic range ( note 18 ) fs=48khz (a - weighted) 100 106 db fs= 96 khz 101 s/n fs=48khz (a - weighted) 100 106 db fs= 96 khz 101 inter - channel isolation (f=1khz) ( note 19 ) 90 110 db dc accuracy channel gain mismatch 0.0 0.5 db analog out put out put voltage ( note 20 ) 2.28 2.51 2.74 vp - p load resistance 10 k load capacitance 30 pf note 18 . s/(n+d) when - 60db fs signal is applied. note 19 . indicates i nter - channel isolation between lch and rch of dac w hen C 1dbfs si g nal is input. note 20 . full - scale output voltage. the output voltage is proporti onal to avdd (avdd x 0. 76 ). [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 17 - dc characteristics (ta= - 40 to 85 ? c , avdd=3.3v, dvdd=1.2v, tvdd=1.7 to 3.6v, avss=dvss=0v) parameter symbol min typ max unit high level input voltage vih 80%tvdd v low level input voltage vil 20%tvdd v scl, sda high level input voltage vih 70%tvd d v scl, sda low level input voltage vil 30%tvdd v dmdat1, dmdat2 high level input voltage (dmic1, dmic2 bit = ? ? 2.0v ? ? ? ? ? k @3.3v ) . power consumptions ( ta=25 ? c , avdd=3.0 to 3.6v (typ=3.3v, max=3.6v), tvdd=1.7 to 3.6v (typ=3.3v, max=3.6v), dvdd=1.1 4 to 1.3v (typ=1.2v, max=1.3v), avss=dvss=0v ) parameter min typ max unit power consumptions in operation 1 ( note 25 ) (ldoe pin = in= l ) in= l ) s hands free program.) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 18 - digital filter characteritics 1. adc (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd=1.1 4 to 1. 3 v, avss=dvss=0v, fs=48khz ( note 26 )) parameter symbol min typ max unit passband ( note 27 ) +0.14db ~ ? s fs ( system s ampling rate) . the characteristic of the high pass filter is not included. note 27 . the passband is from dc to 18.9 khz when fs=48khz. note 28 . the stopband is 28khz to 3.044mhz when fs=48khz. note 29 . when fs = 48khz, the analog modulator samples the input signal at 3.072mhz. there is no att enuation of an input signal in band (n x 3.072mhz 21.99 khz; n=0, 1, 2, 3) of integer times of the sampling frequency by the digital filter. 2. dac (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvd d=1. 7 t o 3.6v, dvdd=1.1 4 to 1. 3 v, avss=dvss=0v, fs=48khz) paramete r symbol min t yp max unit passband ( note 30 ) (0.05db) pb 0 21.7 khz ( - 6.0db) 24 khz stopband ( note 30 ) sb 26.2 khz passband ripple pr 0.0 5 db stopband att enuation sa 64 db group delay (ts=1/fs) ( note 31 ) gd 24 ts digital filter + analog filter amplitude characteristics 20hz to 20.0khz 0.5 db note 30 . the passband and stopband freq uencies are proportional to fs (system sampling rate) , and represents pb=0.4535 fs(@ ? 0.05db) and sb=0.5465 fs , respectively. note 31 . the digital filter delay is calculated as the time from setting data into the input register until an analog signal is output. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 19 - switching characteristics 1. system clock (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd=1.1 4 to 1. 3 v, avss=dvss=0v, cl=20pf) parameter symbol min t yp max unit a) with a crystal oscill a tor: ckm[2:0]bits=0h fxti 11.2896 12.288 mhz ckm [2:0]bits=1h fxti 16.9344 18.432 mhz b) with an external clock duty cycle 40 50 60 % ckm[2:0]bits=0h,2h fxti 11.0 11.2896 12.288 12.4 mhz ckm[2:0]bits=1h fxti 16.5 16.9344 18.432 18.6 mhz lrck frequency ( note 32 ) fs 8 48 96 khz bick frequency ( note 33 ) tdm256 bit = 6.2 mhz tdm256 bit = 12.3 mhz note 32 . rck frequency and sampling rate (fs) should be the same. note 33 . when bick is the source of the master clock, it should be synchronized to lrck and have stable frequency. figure 4 . system clock timing 1/fxti 1/fxti vih vil xti 1/fs 1/fs vih vil tbclkl tbclkh 1/fbclk 1/fbclk vih vil tbclk=1/fbclk txti=1/fxti ts=1/fs lrck bick [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 20 - 2. power down (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd=1 .1 4 to 1. 3 v, avss=dvss=0v) parameter symbol m in typ max unit pdn pulse width ( note 34 ) trst 600 ns note 34 . the pdn pin must be set l when power up the ak7755. figure 5 . reset timing 3. serial data interface sdin1, sdin2, sdout1, sdout2, sdout3 (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd=1.1 4 to 1. 3 v, avss=dvss=0v, cl=20pf) parameter symbol min typ max unit slave mode delay time from bick bick delay time from bick bick 12 ns serial data input latch setup time tbsids 2 0 ns serial data inp ut latch hold time tbsidh 2 0 ns delay time from lrck to serial data output ( note 36 ) tlrd 2 0 ns delay time from bick or sdinn sdoutn (n=1, . note 36 . except i 2 s . note 37 . when the polarity of bick1 is inverted, delay time is from bick1 . figure 6 . serial interface delay time from sdinn to sdoutn output vil trst pdn vih d vil d t iod s dinn n=1,2 50%tvdd vih d sd out nn n=1,2 ,3 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 21 - 3 - 1. slav e mode figure 7 . serial interface input timing in slave mode figure 8 . serial interface output timing in slave mode 3 - 2. master mode figure 9 . serial interface input timing in master mode figure 10 . serial interface output timing in master mode tbsids tmbl tmbl d 50% t vdd d lrc k bick vih d vil d tbsidh sdinn n=1,2 50% t vdd d tlrd d 50% t vdd d 50% t vdd d tbsod d tlrd d tbsod d 50% t vdd d lrck bick sdoutn n=1,2,3 tbsids tblrd tlrbd d vih d l rck bick vil d vih d vil d vih d vil d tbsidh s dinn n=1,2 tlrd d vih d lrck bick vil d vih d vil d sdoutn n=1,2 ,3 50% t vdd d tbsod d tlrd d tbsod d [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 22 - 4. spi interface 4 - 1. clock reset (ckrestn bit = 0 ) (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd=1.1 4 to 1. 3 v, avss=dvss=0v , cl=20pf) parameter symbol min typ max unit microcontroller interface signal sclk frequency fsclk 3.5 mhz sclk low level width tsclkl 120 ns sclk high level wid th tsclkh 120 ns microcontroller pdn rqn sclk sclk csn 4 - 2. pll clock (ckrestn bit = 1 ) (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd= 1.1 4 to 1. 3 v, avss=dvss=0v , cl=20pf) parameter symbol min typ max unit microcontroller interface signal sclk frequenc y fsclk 7 mhz sclk low level width tsclkl 60 ns sclk high level width tsclkh 60 ns microcontroller pdn rqn sclk sclk csn 1 from 0 . [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 23 - figure 11 . spi interface timing 1 figure 12 . spi in terface timing 2 (microcontroller ak7755 ) figure 13 . spi interface timing 3 ( ak7755 microcontroller) tsclkh tsclkl 1/fsclk 1/fsclk sclk vih vil vih vil vih vil trst pd n csn tirrq twrqh tsis tsih tscw tscw twsc tscw cs n si vih vil vih twsc sclk vil vih vil tsos tsoh sclk vil vih so vih vil [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 24 - 5. i 2 c - bus interface (ta= - 40 to 85 ? c ; avdd=3.0 to 3.6v, tvdd=1.7 to 3.6v, dvdd= 1.1 4 to 1. 3 v, avss=dvss=0v, cl=20pf) parameter sym bol min typ max unit i2c timing scl clock frequency fscl 400 k hz bus free time between transmissions tbuf 1.3 ? ? ? ? ? ? ? ? ? ? figure 14 . i 2 c bus interface timing 6. digital mi crophone interface (avdd=3.0 ~ 3.6v, t vdd= 1.7~ 3.6v, dvdd=1. 14~ 1. 3 v, avss=dvss=0v, ta= - 4 0 ? c ~ 85 ? c ; cl= 10 0pf) parameter symbol min typ max unit dmdat 1, dmdat2 serial data input latch setup time tdmds 50 ns serial data input latch hold time tdmdh 0 ns d mclk1, dmclk2 clock frequency ( note 40 ) fdmck 0.5 64fs 6.2 mhz duty cycle ddmck 40 50 60 % rise time tdmckr 10 ns fall time tdmckf 10 ns note 40 . clock frequency is determin ed by the sampling rate (fs) selected by dfs[2:0] bits. thigh scl sda vih tlow tbuf t hd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 2 5 - figure 15 . digital microphone interface timing wave form tdmck 65% a vdd dmclk 1/2 35% a vdd tdmckl 50 % a vdd fdmck = 1 / tdmck ddmck = 100 x tdmkl / tdmck tdmckr tdmckf dmclk 1/2 50% a vdd dmdat 1/2 tdmds vih 2 vil 2 tdmdh dmclk 1/2 50% a vdd dmdat 1/2 tdmds vih 2 vil 2 tdmdh d clk p 1 , dclkp 2 bit = 1 d clk p1, dclkp2 bit = 0 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 26 - 9. functional description system clock master/slave mode switching, clock source pin select for internal master clock (mclk) generating clock (iclk) , and iclk frequency change are controlled by ckm [2:0] clock mode select bits. ckm[2:0] bits can only be set during clock reset. ckm mode ckm [ 2 :0] master slave iclk source sampling frequency fs ( note 41 ) input pin(s) required for system clock use of crystal oscillator 0 000 master xti dfs[2:0]bits xti (12.288mhz) available 1 001 master xt i dfs[2:0]bits xti(18.432mhz) available 2 010 slave xti dfs[2:0]bits xti(12.288mhz), bick, lrck not available 3 011 slave bick dfs[2:0]bits bick, lrck not available 5 101 slave bick fs=16khz fixed bick, lrck(fs=8khz) not available note 41 . the sampling frequency is set by dfs[ 2 :0] bits (cont 0 0). the bick frequency is set by bitfs[1:0] bits. note 42 . in ckm mode 2, xti, bick and lrck must be synchronized but the phase is not critical. note 43 . ckm mode5 is the mode that operates dsp, adc and dac by 16khz sampling frequency when lrck sampling frequency is 8khz . the bick sampling frequency for lrck is set by bitfs[1:0] bit s. 1. relationship between mclk generating clock (iclk) and mclk figure 16 . relation ship between iclk and mclk 2. sampling frequency select fs mode dfs[2:0] fs : sampling frequency 0 000 8khz 1 001 12khz (11.025khz) 2 010 16khz 3 011 24khz (22.05khz) 4 100 3 2khz 5 101 48khz (44.1khz) 6 110 96khz (88.2khz) 7 111 n/a ckm mode 0/1/2 (mclk source ) xti pin divider refclk pll mclk iclk ckm mode 3 /5 (mclk source ) b ick pin divider refclk pll mclk iclk [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 27 - 2 - 1. master mode ( ckm mode 0, 1 : using xti input clock ) fs: sampling frequency ckm mode ckm [2:0] xti input frequency range (mhz) use of chrystal oscillator fs:48khz series fs:44.1khz ser ies 0 000 12.288mhz 11.2896mhz 11.0 to 12.4 available 1 001 18.432mhz 16.9344mhz 16.7 to 18.6 available input system clock to the xti pin by setting bitfs[1:0] bits . the internal counter which is synchronized to xti generates lrck(1fs) and bick( 64fs, 48fs, 32fs , 256fs ). bick frequency can be selected by bitfs[1:0] bits. the bick output will be in two different frequencies if setting bitfs[1:0] bits = 1h (48khz) when the sampling freq uency is 12khz, 24khz, 48khz or 96khz (dfs[2:0]). lrck and bick are n ot output during system reset. figure 17 . using crystal oscillator ( ckm mode 0 / 1 ) using external clock ( ckm mode 0 / 1 ) 2 - 2. slave mode 1 ( ckm mode 2 : xti input clock fs: sampling frequency ckm m ode ckm [2:0] xt i input frequency range use of chrystal oscillator fs:48khz fs:44.1khz (mhz) 2 010 12.288mhz 11.2896mhz 11.0 to 12.4 not available required system clocks are xti, lrck and bick. xti and lrck must be synchronized, but the phase b e t ween these clocks is not important. the system sampling rate is controlled by dfs[2:0] bits. the sampling frequency of bick is set by bitfs[1:0] bits. 2 - 3. slave mode 2 ( ckm mode 3 : bick input clock ) in ckm mode 3 , required system clocks are bick and l rck. in this mode, bick is used for clock source instead of xti. this clock is multiplied directly by a pll to generate the master clock (mclk). t herefore bick with two different frequencies can not be used. bick and lrck must be synchronized. set bick freq uency for lrck by bitfs[1:0] bits. the sampling rate is determined by dfs[2:0] bits setting . in applications which do not need the xti pin of the ak775 5 , leave this pin open . ak77 55 ak77 55 xto xti xto xti external clock [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 28 - 2 - 4. slave mode 3 ( ckm mode 5: bick input clock) ckm mode5 is the mode that o perates dsp, adc and dac by 16khz sampling frequency when lrck sampling frequency is 8khz. set bick frequency against lrck by bitfs[1:0] bits. each sampling frequency is fi x ed (lrck = 8khz, dsp/adc/dac = 16khz). figure 18 . slave mode3 (ckm mode5) sampling frequency setting fs: sampling frequency dfs bitfs bick frequency [2:0] fs [1:0] bick 44.1khz series 48khz series 0 h 8khz 0 h 64fs 470.4khz 512khz 0 h 8khz 1 h 48fs 352.8khz 384khz 0 h 8khz 2 h 32fs 2 35.2khz 256khz 0 h 8khz 3 h 256 fs 1881.6khz 2048 khz 1 h 12khz 0 h 64fs 705.6khz 768khz 1 h 12khz 1 h 48 fs n/a n/a 1 h 12khz 2 h 32fs 352.8khz 384khz 1 h 12 khz 3 h 256 fs 2822.4 khz 3072khz 2 h 16khz 0 h 64fs 940.8khz 1024khz 2 h 16khz 1 h 48fs 705.6khz 768khz 2 h 1 6khz 2 h 32fs 470.4khz 512khz 2 h 16khz 3 h 256 fs 3763.2 khz 4096 khz 3 h 24khz 0 h 64fs 1.4112mhz 1.536mhz 3 h 24khz 1 h 48fs 1058.4mhz 1.152mhz 3 h 24khz 2 h 32fs 705.6khz 768khz 3 h 24khz 3 h 256 fs 5.6448 mhz 6.144mhz 4 h 32khz 0 h 64fs 1.8816mhz 2.048mhz 4 h 32k hz 1 h 48fs 1.4112mhz 1.536mhz 4 h 32khz 2 h 32fs 0.9408mhz 1.024mhz 4 h 32 khz 3 h 256 fs 7.5264m hz 8.192m hz 5 h 48khz 0 h 64fs 2.8224mhz 3.072mhz 5 h 48khz 1 h 48fs 2.1168mhz 2.304mhz 5 h 48khz 2 h 32fs 1.4112mhz 1.536mhz 5 h 48khz 3 h 256 fs 11.2896 mhz 12.288mhz 6 h 96khz 0 h 64fs 5.6448mhz 6.144mhz 6 h 96khz 1 h 48fs 4.2336mhz 4.608mhz 6 h 96khz 2 h 32fs 2.8224mhz 3.072mhz 6 h 96khz 3 h 256 fs 22.5792 mhz 24.576mhz 7 h n/a l rck bick sdin1 sdout1 (fs=8khz) ak77 55 16k/8k converte r dsp /adc/dac (fs=16khz) sdin2 sdout2 sdout3 (fs=16khz) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 29 - figure 19 . bitfs[1:0] bits = 0 h(64fs) ( lrif[1:0]bits = 0 h ) figure 20 . bitfs[ 1:0] bit s= 1h(48fs) ( lrif[1:0]bits = 0 h ) figure 21 . bitfs[1:0] bits = 2h(32fs) ( lrif[1:0]bits = 0 h ) refer to figure 40 and figure 42 when bitfs[1:0] bits = 3h (256fs). left ch l rck b ick right ch 32 bick 32 bick bitfs [1:0] bit s = 0 h @( lri f[1:0] bits = 0 h ) left ch l rck b ick right ch 24 bick 24 bick bitfs [1:0] bit s = 1 h @( lri f[1:0] bits = 0 h ) left ch l rck bi ck right ch 16 b i ck 16 b i ck bitfs[1:0] bits = 2 h @(lrif[1:0] bits = 0h) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 30 - control register settings control registers are reset by a power down release (pdn pin = l h ) . since control registers cont00 - cont01 are related to clock generation, they must be changed during clock reset (ckrstn bit (cont01: d0) = 0). cont1 2 - c ont1 9 can be written during operation. the other control registers must be changed during clock reset or system reset (cr e s e tn bit (cont0f: d3) and dspr e s e tn bit (cont0f: d2) = 0) to avoid errors and noises. cont0d: d6, cont1a: d4, cont26: d0 and cont 2a: d7 bits must be set to 1 during system reset. once these bits are set to 1 , the value will be kept until power down the ak7755 (pdn pin = l ). do not write to the cont1f - cont25, cont27 - cont29 and cont2b - cont3f registers. cont00 - cont1 e , cont26, c ont2a name d7 d6 d5 d4 d3 d2 d1 d0 default cont00 0 ckm[2] ckm[1] ckm[0] aine dfs[2] d fs[1] d fs[0] 00h cont01 jx2e lrdown bitfs[1] bitfs[0] clks[2] clks[1] clks[0] ckresetn 00h cont02 tdm256 bckp lr if[1] lr if[0] tdmmode[1] tdmmode[0] jx1e jx0e 00h cont 03 dif2[1] dif2[0] dof2[1] dof2[0] bank[3] bank[2] bank[1] bank[0] 00h cont04 drms[1] drms[0] dram[1] dram[0] pomode 0 wavp[1] wavp[0] 00h cont05 accram clrn jx3e firmode1 firmode2 submode1 submode2 memdiv[1] memdiv[0] 00h cont06 dem[1] dem[0] difda[1] difda[0] 0 dif1[2] dif1[1] dif1[0] 00h cont07 dof4[1] dof4[0] dof3[1] dof3[0] 0 dof1[2] dof1[1] dof1[0] 00h cont08 seldai[1] seldai[0] seldo 3 [1] seldo 3 [0] seldo2[1] seldo2[0] selmix[1] selmix[0] 00h cont09 difr inr difl inl lo3sw3 lo3sw2 lo3sw1 selmix[2 ] 00h cont0a clkoe bi ck e lrcke 0 0 out 3 e out2e out1e 00h cont0b 0 0 0 0 0 0 0 0 00h cont0c dsm 0 atspad atspda 0 seldo1[2] seldo1[1] seldo1[0] 00h cont0d sto 1 0 0 0 0 0 dls 8 0h cont0e pmadr pmadl pmad2l pmlo3 pmlo2 pmlo1 pmdar pmdal 00h cont0f 0 0 p ml1 lrdetn cresetn dsp resetn pmad2r dlrdy 00h cont10 wdten crce plllocke socfg selsto 0 0 ckadjen 00h cont 1 1 ckadj[7] ckadj[6] ckadj[5] ckadj[4] ckadj[3] ckadj[2] ckadj[1] ckadj[0] 00h cont12 mgnr[3] mgnr[2] mgnr[1] mgnr[0] mgnl[3] mgnl[2] mgnl[1] mgnl[ 0] 00h cont13 lign [ 3 ] lign [2] lign [1] lign[0] lov ol3 [3] lov ol3 [2] lov ol3 [1] lov ol3 [0] 00h cont14 lov ol2 [3] lov ol2 [2] lov ol2 [1] lov ol2 [0] lov ol1 [3] lov ol1 [2] lov ol1 [1] lov ol1 [0] 00h cont15 voladl[7] voladl[6] voladl[5] voladl[4] voladl[3] voladl[2] volad l[1] voladl[0] 30h cont16 voladr[7] voladr[6] voladr[5] voladr[4] voladr[3] voladr[2] voladr[1] voladr[0] 30h cont17 volad 2l [7] volad 2l [6] volad 2l [5] volad 2l [4] volad 2l [3] volad 2l [2] volad 2l [1] volad 2l [0] 30h cont18 voldal[7] voldal[6] voldal[5] voldal[ 4] voldal[3] voldal[2] voldal[1] voldal[0] 18h cont19 voldar[7] voldar[6] voldar[5] voldar[4] voldar[3] voldar[2] voldar[1] voldar[0] 18h cont1a admute ad2mute damute 1 adrcre adrcle micrzce miclzce 00h cont1b amgnr[3] a mgnr[2] a mgnr[1] a mgnr[0] amgnl[3 ] a mgnl[2] a mgnl[1] a mgnl[0] 00h cont1 c 0 0 0 0 0 0 0 0 00h cont1 d volad 2r [7] volad 2r [6] volad 2r [5] volad 2r [4] volad 2r [3] volad 2r [2] volad 2r [1] volad 2r [0] 30h cont1 e dmic1 dmclkp1 dmclke1 dmic2 dmclkp2 dmclke2 0 0 00h cont26 0 0 0 0 0 0 0 1 00h cont2a 1 0 0 0 0 0 0 0 00h [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 31 - cont00 : clock setting 1 , analog input setting write during clock reset. w r name d7 d6 d5 d4 d3 d2 d1 d0 default c0h 40h cont00 0 ckm[2] ckm[1] ckm[0] aine dfs[2] dfs[1] dfs[0] 00h d6, d5, d4: ckm[ 2 :0] clock mode setting ckm mo de ckm [2:0] master slave main clock fs system clock 0 000 master xti=12.288mhz fixed fs=8~96khz xti (default) 1 001 master xti=18.432mhz fixed fs=8~96khz xti 2 010 slave xti=12.288mhz fixed fs=8~96khz xti, bick, lrck 3 011 slave bick fs=8~96khz bic k, lrck 5 101 slave bick fs=16khz bick, lrck(fs=8khz) tdm256 bit (cont02: d7) = 1 cannot be used in ckm mode5. d3: aine analog input setting (in1/inp1, in2/inn1, in3/inp2, in4/inn2 pin) 0: not using analog input (default) 1: using analog input set aine bit to 1 first before other control register settings when using the in1/inp1, in2/inn1, in3/inp2 and in4/inn2 pins as analog inputs. the ak7755 starts charging to a capacitor connected to each pin by t his s etting. set aine bit to 0 when u sing digital microphones (dmic1 or dmic2 bit (cont1e: d7, d4) = 1 ). d2, d1, d0: dfs[2:0] sampling frequency dfs mode dfs[2:0] fs 0 000 8khz (default) 1 001 12khz 2 010 16khz 3 011 24khz 4 100 32khz 5 101 48khz 6 110 96khz 7 111 n/a multiply 44.1/48 to calculate the values for mu l ti p le sampling frequencies of 44.1khz . write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 32 - cont01 : clock setting 2 and jx2 setting write during clock reset. w r name d7 d6 d5 d4 d3 d2 d1 d0 default c1h 41h cont01 jx2e lr down bit fs [1] bitfs [0] clks [2] clks [1] clks [0] ck resetn 00h d7: jx2 e external conditional jump 2 enable 0: jx2 is disabled (default) , no. 14 - pin output (sdout3) when out3e bit (cont0a:d2) = 1 1: jx2 is enabled, no. 14 - pin input d6: lrdown lrck sampling frequency select 0: lrck s ampling frequency set by dfs[2:0] bits (cont00: d2 - d0) . (default) 1: lrck half frequency of the set ting value by dfs[2:0] bits the ak7755 can output the lrck which is half frequency of the setting value by dfs[2:0] bits in mast er mode (ckm mode 0, 1 (cont00: d6 - d4) ) . this mode is used when lrck/bick/sdin1/sdout1 is driven by fs= 8khz while the ak7755 i s driven by fs= 16khz in master mode . lrdown bit = 1 cannot be set when tdm256 bit (cont02: d7) = 1 . d5, d4: bitfs[1:0] bick fs select bitfs mode bitfs [1:0] bick note 0 00 64fs 512khz(@fs=8khz),3.072mhz(@fs=48khz) (default) 1 01 48fs 384khz(@fs=8khz),2.304mhz(@fs=48khz) 2 10 32fs 256khz(@fs=8khz),1.536mhz(@fs=48khz) 3 11 256fs 2.048m hz(@fs=8khz), 12.288 mhz(@fs= 48 khz) t his setting is valid in both slave and master modes. set the bick input sampling frequency against lrck , in slave mode ( ckm2, 3 and 5 ) . set the bick output sampling frequency against lrck in master mode ( ckm 0 and 1 ) . the bick output will be in two differ ent frequencies if setting bitfs[1:0] bits = 1h (48khz) when the sampling frequency is 12khz, 24khz, 48khz or 96khz (dfs[2:0]). d3, d2, d1: clks[2:0] clko output clock select clks mode clks[2:0] fs=48khz fs=44.1khz 0 000 12.288mhz 11.2896mhz (default) 1 001 6.144mhz 5.6448mhz 2 010 3.072mhz 2.8224mhz 3 011 8.192mhz 7.5264mhz 4 100 4.096mhz 3.7632mhz 5 101 2.048mhz 1.8816mhz 6 110 256fs 256fs 7 111 xti or bick xti or bick d0: ckresetn clock reset 0: clock reset (default) 1: clock reset r elease [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 33 - cont02 : serial data format, jx 1, 0 s etting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c2h 42h cont02 tdm256 bckp lrif[1] lrif[0] tdm mode[1] tdm mode[0 ] jx1e jx0e 00h d7: tdm256, tdm select 0: normal interface (default) 1: tdm interface bick is fixed to 256fs . set bitfs[1:0] bits = 3h ( cont01: d5, d4) . format is selected by lrif[1:0] bits setting (cont02: d5, d4). in this mode, ckm mode 5 (cont00: d6 - d4) is not available. tdm256 bit cannot be set to 1 when lrdown bit (cont00: d6) = 1 . in tdm mode, a 96khz sampling frequency is not available. dfs[2:0] bits (cont00: d2 - d0) setti ng must be lower than 5h (48khz). d6: bckp bick edge select bckp bit bick edge referenced to lrck edge 0 falling (fe) (default) 1 rising (re) d5, d4: lrif[1:0] lrck i/f format mode lrif[1:0]bit digital i/f format 0 00 standard ( msb justified / lsb justified ) (default) 1 01 i 2 s compatible 2 10 pcm short frame 3 11 pcm long frame in standard format mode, msb justified and 24/20/16 bit lsb justified formats are selectable by dif1 bits (cont06: d2 - d0) , dif 2 bit s (cont03: d7, d6), di f da bit s (cont06: d5, d4), dof1 bit s (cont07: d2 - d0), dof 2 bit s (cont03: d5, d4), dof 3 bit s (cont07: d5, d4), and dof 4 bit s (cont07: d7, d6) . in ot her modes, msb justified form at s hould be selected by dif1 - 2 bits, daf bit and dof1 - 4 bits. d 3, d2 : tdmmode[1:0] dspdin3, dspdin4 input source select (valid when tdm256bit = 1 ) mode tdmmode [1:0] dspdin4 lch dspdin4 rch dspdin3 lch dspdin3 rch 0 0 0 sdin1 slot7 sdin1 slot8 sdin1 slot5 sdin1 slot6 (default) 1 0 1 sdoutad lch sdoutad rch sdin1 slot5 sdin1 slot6 2 10 sdoutad lch sdoutad rch sdoutad 2 lch sdoutad2 rch 3 11 n/a n/a n/a n/a d1: jx1e exter nal conditional j ump1 enable 0: jx1 is invalid (default) 1: jx1 is valid d0: jx 0e external conditional jump0 enable 0: jx0 is invalid (default) 1: jx0 is valid [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 34 - cont03 : delay ram , dsp input / output setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c3h 43h cont03 0 0 0 0 bank[3] bank[2] bank[1] bank[0] 00h d 7 , d 6: dif2 [1:0] ds p din2 input format select dif2 mode dif2 [1:0] input data format 0 00 msb (24 - b it ) (default) 1 01 lsb 24 - b it 2 10 lsb 20 - b it 3 11 lsb 16 - b it set 00 for i 2 s compatible, pcm short and pcm long format s . set 11 when bitfs[1:0] bits (cont01: d5, d4 ) = 2h (32fs) . d 5 , d 4: dof2 [1:0] dsp dout2 output format select dof2 mode dof2 [1:0] output data format 0 00 msb (24 - b it ) (default) 1 01 lsb 24 - b it 2 10 lsb 20 - b it 3 11 lsb 16 - b it set 00 for i 2 s compatible, pcm short and pcm long format s . set 1 1 when bitfs[1:0] bits = 2h (32fs). d3, d2, d1, d0: bank[3:0] dlram mode setting dlram par ti tion mode bank [3:0] delay ram bank1 bank0 linear 20.4f ring 20.4f 0 0000 0 8192 words (default) 1 0001 1024 words 7168 words 2 0010 2048 words 614 4 words 3 0011 3072 words 5120 words 4 0100 4096 words 4096 words 5 0101 5120 words 3072 words 6 0110 6144 words 2048 words 7 0111 7168 words 1024 words 8 1000 8192 words 0 9 - 15 1001 1111 n/a [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 35 - cont04 : data ram , cram setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c4h 44h cont04 drms[1] drms[0] dram[1] dram[0] pomode 0 wavp[1] wavp[0] 00h d7, d6: drms[1:0] data ram size setting dram mode drms [1:0] dsp data ram bank1 bank0 memory size[words] memory size[words] 0 00 512 15 36 (default) 1 01 1024 1024 2 10 1536 512 3 11 n/a d5, d4: dram[1:0] data ram addressing mode setting addressing mode dram [1:0] dsp data ram bank1 dp1 bnak0 dp0 0 00 ring ring (default) 1 01 ring linear 2 10 linear ring 3 11 linea r linear d3: pomode dlram pointer 0 select 0: dbus immediate (default) 1: ofreg d1, d0 : wavp[1:0] cram memory assignment wavp mode wavp[1 :0] fft point number 0 0 0 33word 128 (default) 1 0 1 65word 256 2 1 0 129word 512 3 1 1 257word 1024 writ e 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 36 - cont05 : accelerator setting , jx3 setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c5h 45h cont05 accram clrn jx3e fir mode1 fir mode2 sub mode1 sub mode2 mem div[1] mem div[0] 00h d 7: accramclrn accelerator cram clear se tting 0: accelerator cram is cleared by 0 data after releasing reset . ( default) 1: accelerator cram is not cleared after releasing reset. d6: jx3e external conditional j ump3 enable 0: jx3 disable (defau lt) , no. 1 5 pin output (sdout2) when out2e bit (cont0 a:d1) = 1 1: jx3 enable , no. 15 pin input d 5: firmode1 accelerator c h1 operation select 0: adaptive filter (default) 1: fir filter d 4: firmode2 accelerator c h2 operation select 0: adaptive filter (default) 1: fir f i lter d3: submode1 accelerator c h 1 mode select 0: fullband (default) 1: subband d2: submode2 accelerator ch2 mode select 0: fullband (default) 1: subband d1, d0: memdiv[1:0] accelerator memory select mode memdiv[1:0] ch 1 ch 2 0 00 2048 - (default) 1 01 1792 256 2 10 1536 512 3 1 1 1024 1024 write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 37 - cont06 : dac de - emphasis, dac and dsp input format s e t ting s w r name d7 d6 d5 d4 d3 d2 d1 d0 default c6h 46h cont06 dem[1] dem[0] difda[1] difda[0] 0 dif 1 [ 2 ] dif1[1] dif1[0] 00h d 7 , d 6: dem[1:0] dac d e - emphasis setting (50/15s) dem mode dem[1:0] sampling frequency fs 0 00 off (default) 1 01 48khz 2 10 44.1khz 3 11 32khz d5, d4: difda[1:0] dac input format select difda mode difda[1:0] input data format 0 00 msb justified (24 - b it ) (default ) 1 01 lsb justified 24 - b it 2 10 lsb justified 20 - b it 3 11 lsb justified 16 - b it set 00 for i 2 s compatible, pcm short and pcm long format s. set 11 when bitfs[1:0] bits (cont01: d5, d4) =2h (32fs) . set 00 when connecting mixout or dsp - dout4 to d ac input . d2, d 1 , d 0: dif1 [ 2 :0] dsp din1 input format select dif1 mode dif1 [ 2 :0] input data format 0 0 00 msb (24 - b it ) (default) 1 0 01 lsb 24 - b it 2 0 10 lsb 20 - b it 3 0 11 lsb 16 - b it 4 100 msb 8 - b it 000 for i 2 s compatible, pcm short and pcm long formats. set 011 when bitfs[1:0]=2h (32fs) . write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 38 - cont07 : dsp ou tp ut format setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c7h 47h cont07 dof 4 [1] dof 4 [0] dof3[1] dof3[0] 0 dof 1 [ 2 ] dof1[1] dof1[0] 00h d 7 , d 6 : dof 4 [1:0] dsp dout 4 output format select dof 4 mode dof 4 [1:0] output data format 0 00 msb justified (24 - b it ) (default) 1 01 lsb justified 24 - b it 2 10 l sb justified 20 - b it 3 11 lsb justified 16 - b it set 00 for i 2 s compatible, pcm short and pcm long format s. set 11 when bitfs[1:0] bits (cont01: d5, d4) =2h (32fs) . set 00 when connecting to the dac. d5, d4: dof3[1:0] dsp dout3 output format selec t dof3 mode dof3[1:0] output data format 0 00 msb justified (24 - b it ) (default) 1 01 lsb justified 24 - b it 2 10 lsb justified 20 - b it 3 11 lsb justified 16 - b it set 00 for i 2 s compatible, pcm short and pcm long formats . set 11 when bitfs[1:0] bits =2h (32fs) . d2, d 1 , d 0: dof1 [ 2 :0] dsp dout1 output format select dof1 mode dof1 [ 2 :0] output data format 0 0 00 msb (24 - b it ) (default) 1 0 01 lsb 24 - b it 2 0 10 lsb 20 - b it 3 0 11 lsb 16 - b it 4 100 msb 8 - b it 000 for i 2 s compatible, pcm short and pcm long formats. set 011 when bitfs[1:0] bits =2h (32fs) . write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 39 - cont08 : d ac input , sdout2 / 3 output , digital mixer input se tting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c8h 48h cont08 seldai [1] seldai [0] seldo3 [1] seldo3 [0] seldo2 [1] seldo2 [0] selmix [1] selmix [0] 00h d7, d6: seldai[1:0] dac input select seldai mode seldai[1:0] input data 0 00 dsp dout4 (default) 1 01 mixout 2 10 sdin2 3 11 sdin1 set difda[1:0] bits (cont06: d5, d4) = 0h when selecting dsp dout4 or mixout. d5, d4: seldo3[1:0] sdout3 pin output select seldo3 mode seldo3[1:0] output data 0 00 dsp dout3 (default) 1 01 mixout 2 10 dsp dout4 3 11 sdoutad 2 the output format is fixed to msb 24 - bit when selecting sdoutad 2 or mixout. d3, d2: seldo2[1:0] sdout2 pin output select seldo2 mode seldo2[1:0] output data 0 00 dsp dout2 (default) 1 01 gp1 2 10 sdin2 3 11 s doutad 2 the output fo rmat is fixed to msb 24 - bit when selectin g sdoutad 2 . (cont09 d0), d1, d0: sel mix [ 2 :0] digital mixer input select sel mix mode sel mix [ 2 :0] mixout lch mixout rch 1 00 0 sdoutad lch sdoutad rch (default) 1 0 01 sdoutad lch/2 + sdoutad2 lch/2 sdoutad rch 2 0 10 sdoutad lch sdoutad rch /2 + sdoutad2 rch/2 3 0 11 sdoutad2 lch sdoutad2 r ch 4 100 dsp - dout4 lch sdoutad2 rch 5 101 sdoutad2 lch dsp - dout4 rch 6 110 dsp - dout4 lch sdoutad rch 7 111 sdoutad lch dsp - dout4 rch [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 40 - cont09 : analog input / output setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default c9h 49h cont09 difr inr difl inl lo3sw3 lo3sw2 lo3sw1 selmix[2] 00h d7, d6: difr, inr adc rch analog input difr bit inr bit adc rch 0 0 in3 (default) 0 1 in4 1 x inp2/inn2 d5, d4: difl, inl adc lch analog input difl bit inl bit adc lch 0 0 in1 (default) 0 1 in2 1 x inp1/inn1 figure 22 . analog input select d 3: lo3sw3 out3 mixing select 3 0: lin off (default) 1: lin on d 2 : lo3sw2 out3 mixing select 2 0: dac rch off (default) 1: dac rch on d 1 : lo3sw1 out3 mixing select 1 0: dac lch off (default) 1: dac lch on figure 23 . out3 output select d 0: sel mix [ 2 ] digital mixer input select refer to cont08 : d1, d0 , se l mix[2:0] bits out1 pin lovol1[3:0] stereo dac lch stereo dac rch out2 pin lovol2[3:0] out3 pin lovol3[3:0] lo3sw1 lo3sw2 lo3sw3 lign [3:0] lin pin mono adc m i x ak7755 in1 /in p1 pin ak7755 mic - amp rch i n2 /in n1 pin in 4 /in n2 pin in 3 /in p2 pin adc lch inl bit difl bit mic - amp lch adc rch inr bit difr bit [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 41 - cont0a : clk and sdout output setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default cah 4ah cont0a clkoe bickoe lrckoe 0 0 out3e out2e out1e 00h d7: clkoe clko pin setting 0: clko= l (default) 1: clko output enable d6: bickoe bick pin o utput setting 0: bicko= l (default) 1: bicko output enable this setting is invalid in slave mode (ckm mode 2, 3, and 5 (cont00: d6 - d4) ). d5: lrckoe lrck pin output setting ( master mode ) 0: lrcko= l (default) 1: lrcko output enable this setting is in valid in slave mode (ckm mode 2, 3 and 5). d2: out3 e 0: sdout3= l (default) 1: sdout3 output enable valid when jx2e bi t (cont01: d7) = 0 d1: out2e 0: sdout2= l (default) 1: sdout2 output enable valid when jx3e bit (cont05: d6) = 0 d0: out1e 0: sdout1= l (default) 1: sdout1 output enable write 0 into the 0 registers. cont0b : test setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default cbh 4bh cont0b 0 0 0 0 0 0 0 0 00h write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 42 - cont0c : adc , dac volume transitio n time and sdout1 output setting s w r name d7 d6 d5 d4 d3 d2 d1 d0 default cch 4ch cont0c dsm 0 atspad atspda 0 seldo1[2] seldo1[1] seldo1[0] 00h d7: dsm delta sigma module sampling clk setting 0: dsmclk 256fs (default) 1: dsmclk 12.288mhz d5: atspad adc volume transition time setting 0: 1/fs (default) 1: 4/fs d4: atspda dac volume transition time setting 0: 1/fs (default) 1: 4/fs d2, d 1 , d 0: seldo1[ 2 :0] sdout1 pin output select seldo1 mode seldo1[ 2 :0] output data 0 0 00 dsp dout1 (default) 1 0 0 1 gp0 2 0 10 sdin1 3 0 11 sdoutad 4 100 eest 5 101 sdoutad 2 6 110 n/a 7 111 n/a the output format is fixed to msb 24 - bit when selecting sdouta d or sdoutad 2 . write 0 into the 0 registers. cont0d : sto status read and eeprom download setti ng w r name d7 d6 d5 d4 d3 d2 d1 d0 default c d h 4 d h cont0 d sto 1 0 0 0 0 0 dls 8 0h d7: sto status output 0: internal error status 1: normal operation (default) this is a read only register. d6: 1 thise bit should be set to 1 during system reset ( cresetn bit (cont0f:d3) = 0 and dspresetn bit (cont0f: d2) = 0 ) . d0: dls start eeprom downloading 0: normal operation (default) 1: start eeprom downloading this setting is valid when the i2csel pin= h . register settings and dsp programs can be down loaded from an external eeprom by setting the exteep pin = h or dls bit = 1 . however , when selecting memory mat (i2csel pin = matsel pin = h ) , download ing cannnot be executed by dls bit. write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 43 - cont0e : adc , dac , lineou t power management w r name d7 d6 d5 d4 d3 d2 d1 d0 default ce h 4e h cont 0e pmadr pmadl pmad2l pm lo3 pmlo2 pmlo1 pm dar pmdal 00h d7 : pmadr power management (mic - amp rch + adc rch) 0: power - down (default) 1: start normal operation after releasing codec r eset ( cresetn bit (cont0f: d3) = 1 ) . d6 : pmadl power management (mic - amp lch + adc lch) 0: power - down (default) 1: start normal operation after releasing codec reset ( cresetn bit = 1 ). d5 : pm ad 2l power management (adc 2 lch ) 0: power - down (default) 1: start normal operation after releasing codec reset ( cresetn bit = 1 ). d 4: pm lo3 lineout 3 power management 0: power - down (default) 1: normal operation d 3: pm lo2 lineout 2 power management 0: power - down (default) 1: normal operation d 2: pm lo1 lineout 1 power management 0: power - down (default) 1: normal operation d 1: pmdar power management (dac rch) 0: power - down (default) 1: start normal operation after releasing codec reset ( cresetn bit = 1 ). d 0: pmdal power management (dac lch) 0: power - down (default) 1: start normal operation after releasing codec reset ( cresetn bit = 1 ). [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 44 - cont0f : reset settings , lineout and digital mic2 rch power management s w r name d7 d6 d5 d4 d3 d2 d1 d0 default cfh 4fh cont0f 0 0 pml1 lrdetn cresetn dspresetn pmad2r dlrdy 00h d 5: pm li li ne - in power management 0: power - down ( default) 1: normal operation d 4: lrdetn slave mode automatic system reset setting 0: lrck detect on (default) 1: lrck detect off when this bit is 0 , if the lrck is stopped or the lrc k phase is shifted mo re than 1/4fs , the ak7755 enters system reset state automatically. d3: cresetn codec reset n 0: codec reset (default) 1: codec reset release codec means the adc and the d ac. d2: dspresetn dsp reset n 0: dsp reset (default) 1: dsp reset release the ak7755 is in system reset state when cresetn bit = 0 and dspresetn bit = 0 . d 1: pm ad2r power managements of adc2 rch ( only when using digital microphone) 0: power - down (default) 1: the ak7755 enters normal operation after releasing codec reset ( cresetn bit = 1 ) . d0: dlrdy dsp download ready 0: normal operation (default) 1: program downloading dsp programs and coefficient data can be downloaded by setting this bit to 1 during clock reset (ckresetn bit = 0 ) or when the main c lock is stopped. this bit must be set to 0 after finishing the downloading. write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 45 - cont 1 0 : function settings w r name d7 d6 d5 d4 d3 d2 d1 d0 default d0h 50h cont 10 wdten crce plllocke socfg selsto 0 0 ckadjen 00h d 7: w dten wdt (watchdog timer) setting 0: wdte enable (default) 1: wdte disa ble d 6: crce crc ( cyclic redundancy check) setting 0: crc disable (default) 1: crc enable d 5: plllocke pll lock detection 0: pll lock disable (default) 1: pll lock enable d4: socf g so pin hi - z select 0: hi - z (default) 1: cmosl d3: selsto sto/rdy pin selecting status out 0: sto (default) 1: rdy d 0: ckadjen clock adjust ment enable 0: ckadj disable (default) 1: ckadj enable write this bit to 1 when setting cont11 ckadj [7:0] bit s. write 0 into the 0 registers. cont 1 1 : dspmclk availability ratio setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d1h 51h cont1 1 ck adj[7]) ck adj[6]) ck adj[5]) ck adj[4]) ck adj[3]) ck adj[2]) ck adj[1]) ck adj[0]) 00h d 7 - d0: ckadj [7:0] dspmclk availability ratio setting availability = (256 - ckadj) / 256 0 0 00_0000 : 100% driving (normal) (default) 0000_0001 : 99.6% driving ? ? ? 1000_0000 : 50% driving ? ? ? 1111_1110 : 0.8% driving 1111_1111: 0.4% driving set cont10 ckadjen bit to 1 wh en using this register. dspmclk must always be more than 10 times of sclk . for example, when sclk is 2mhz, the setting should be lower than 0hd6 (214) since ckadj [7:0] < 256 C ( 2 x 10 x 256 ) / 122.88 = 214.33 . [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 46 - cont12 : microphone gain sett i ng w r name d7 d6 d5 d4 d3 d2 d1 d0 default d2h 52h cont12 mgnr [3] mgnr [2] mgnr [1] mgnr [0] mgnl [3] mgnl [2] mgnl [1] mgnl [0] 00h d7, d6, d5, d4: mgnr[3:0] microphone input rch gain setting mgnr mode mgnr[3:0] microphone input rch gain 0 0000 0db (default) 1 0001 2 db 2 0010 4 db 3 0011 6 db 4 0100 8 db 5 0101 10 db 6 0110 12 db 7 0111 14 db 8 1000 16db 9 1001 18db a 1010 21db b 1011 24db c 1100 27db d 1101 30db e 1110 33db f 1111 36db d3, d2, d1, d0: mgnl[3:0] microphone input lch ga in mgnl mode mgnl[3:0] microphone input lch gain 0 0000 0db (default) 1 0001 2 db 2 0010 4 db 3 0011 6 db 4 0100 8 db 5 0101 10 db 6 0110 12 db 7 0111 14 db 8 1000 16db 9 1001 18db a 1010 21db b 1011 24db c 1100 27db d 1101 30db e 111 0 33db f 1111 36db [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 47 - cont13 : line - in/lineout 3 volume setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d3h 53h cont13 lign[3] lign[2] lign[1] lign[0] lovol3 [3] lovol3 [2] lovol3 [1] lovol3 [0] 00h ? d7, d6, d5, d4: lign[3:0] line - in volume setting li gn mode lign[3:0] line - in volume setting 0 0000 0db (default) 1 0001 - 3db 2 0010 - 6db 3 0011 - 9db 4 0100 - 12db 5 0101 - 15db 6 0110 - 18db 7 0111 - 21db 8 1000 n/a 9 1001 +3db a 1010 +6db b 1011 +9db c 1100 +12db d 1101 +1 5 db e 11 10 +1 8 db f 1111 + 21 db ? d3, d2, d1, d0: lovol3[3:0] line - out 3 volume setting lovol3 mode lovol3[3:0] line - out 3 volume setting 0 0000 mute (default) 1 0001 - 28db 2 0010 - 26db 3 0011 - 24db 4 0100 - 22db 5 0101 - 20db 6 0110 - 18db 7 0111 - 16db 8 1000 - 14db 9 100 1 - 12db a 1010 - 10db b 1011 - 8db c 1100 - 6db d 1101 - 4db e 1110 - 2db f 1111 0db [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 48 - cont14 : line - out 1, line - out 2 volume setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d4h 54h cont14 lovol2 [3] lovol2 [2] lovol2 [1] lovol2 [0] lovol1 [3] lo vol1 [2] lovol1 [1] lovol1 [0] 00h d7, d6, d5, d4: lovol2[3:0] line - out 2 volume setting lovol2 mode lovol2[3:0] lineout 2 volume setting 0 0h mute (default) 1 1h - 28db 2 2h - 26db 3 3h - 24db 4 4h - 22db 5 5h - 20db 6 6h - 18db 7 7h - 16db 8 8h - 14db 9 9h - 12db a ah - 10db b bh - 8db c ch - 6db d dh - 4db e eh - 2db f fh 0db d3, d2, d1, d0: lovol1[3:0] line - out 1 volume setting lovol1 mode lovol1[3:0] lineout 1 volume setting 0 0h mute (default) 1 1h - 28db 2 2h - 26db 3 3h - 24db 4 4h - 22db 5 5h - 20db 6 6h - 18db 7 7h - 16db 8 8h - 14db 9 9h - 12db a ah - 10db b bh - 8db c ch - 6db d dh - 4db e eh - 2db f fh 0db cont15 - 16 - 17 : adc , adc2 lch digital volume setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d5h 55h cont15 vol adl[7] vol adl[6] vol adl[5] vol adl[4] vol adl[3] vol adl[2] vol adl[1] vol adl[0] 30h d6h 56h cont16 vol adr[7] vol adr[6] vol adr[5] vol adr[4] vol adr[3] vol adr[2] vol adr[1] vol adr[0] 30h d 7 h 5 7 h cont1 7 vol ad 2l [7] vol ad 2l [6] vol ad 2l [5] vol ad 2l [4] vol ad 2l [3] vol ad 2l [2] vol ad 2l [1] vol ad 2l [0] 30h refer to 2 - 3. adc , adc2 digital volume . [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 49 - cont1 8 - 1 9 : dac digital volume setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d 8 h 5 8 h cont1 8 vol dal[7] vol dal[6] vol dal[5] vol dal[4] vol dal[3] vol dal[2] vol dal[1] vol dal[0] 18h d 9 h 5 9 h cont1 9 vol dar[7] vol dar[6] vol dar[5] vol dar[4] vol dar[3] vol dar[2] vol dar[1] vol dar[0] 18h refer to 2. dac digital volume . cont1 a : adc/dac mute , adrc and zero - cross settings w r name d7 d6 d5 d4 d3 d2 d1 d0 default d a h 5 a h cont1 a ad mute a d2 mute da mute 1 adrcre adrcle micrzce miclzce 00h d7 : admute adc mute setting 0: stereo adc mute release (default) 1: stereo adc mute d 6: ad m mute adc 2 mute setting 0: adc 2 mute release (default) 1: adc 2 mute d 5: damute da c mute setting 0: dac mute release (default) 1: dac mute d4: 1 thise bit should be set to 1 during system reset ( cresetn bit (cont0f: d3) = 0 and dspresetn bit (cont0f: d2) = 0 ) . d 3: adrcre analog dynamic range control ler rch enable setting 0: adrc rch disable (default) 1: adrc rch enable d 2: adrcle analo g dynamic range controller lch enable setting 0: adrc lch disable (default) 1: adrc lch enable d1: micrzce micgain rch zero - corss enable 0: rch zero - cross detection on (default) 1: rch zero - cross detection off d0: miclzce micgain lch zero - cross enable 0: lch zero - cross detection on (default) 1: lch zero - cross detection off write 0 into the 0 registers. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 50 - cont 1b : microphone gain read register when using adrc w r name d7 d6 d5 d4 d3 d2 d1 d0 default - 5b h cont 1b a mgnr [ 3 ] a mgnr [2] a mgnr [1] a mgnr [0] a mgnl [ 3 ] a mgnl [2] a mgnl [1] a mgnl [0] 00h this register is a read only register. amgnr[3:0] bits will be valid when adrcre bit (cont1a: d 3) = 1 , and amgnl[3:0] wil l be valid when adrcle bit (cont1a: d 2) = 1 . the microphone gain value set by dsp can be readout. cont 1c : test setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default dc h 5c h cont 1c 0 0 0 0 0 0 0 0 00h write 0 into the 0 registers. cont 1d : adc2 rch di gital volume setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d d h 5 d h cont1 d vol ad 2r [7] vol ad 2r [6] vol ad 2r [5] vol ad 2r [4] vol ad 2r [3] vol ad 2r [2] vol ad 2r [1] vol ad 2r [0] 30h refer to 2 - 3. a dc2 digital volume . cont 1e : digital microphone interface setting w r name d7 d6 d5 d4 d3 d2 d1 d0 default d d h 5 d h cont1 d dmic1 dmclkp1 dmclke1 dmic2 dmclkp2 dmclke2 0 0 0 0h d7 : dmic1 digital microphone 1 select 0: not using dmic1 (default) 1: using dmic1 when dmic1 bit = 1 or dmic2 bit = 1 , pin number 3 1~ 34 become digital microphone interface s , and analog input s are not available. d 6: dmclkp1 digital microphone 1 channel setting dmclkp1 dmclk1 pin = d 5: dmclke1 digital microphone 1 clock settin g 0: dmclk1 pin = l (default) 1: dmclk1 64fs (output enable) ? d 4: dmic2 digital microphone 2 select 0: not using dmic2 (default) 1: using dmic2 when dmic1 bit = 1 or dmic2 bit = 1 , pin number 31 ~ 34 become digital microphone interfaces, and analo g inputs are not available. ? d 3: dmclkp2 digital microphone 2 channel setting dmclkp2 dmclk2 pin = ? d 2: dmclke2 digital microphone 2 clock setting 0: dmclk2 pin = l (default) 1: dmclk1 64fs (ou tput enable) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 51 - do not write data into cont21 - cont25. cont26 w r name d7 d6 d5 d4 d3 d2 d1 d0 default e6 6 6 h cont26 0 0 0 0 0 0 0 1 00 h d0: 1 thise bit should be set to 1 during system reset (cresetn bit (cont0f: d3) = 0 and dspresetn bit (cont0f: d2) = 0 ). write 0 into the 0 registers. do not write data into cont27 - cont29. cont2a w r name d7 d6 d5 d4 d3 d2 d1 d0 default ea 6 a h cont2a 1 0 0 0 0 0 0 0 00 h d7: 1 thise bit should be set to 1 during system reset (cresetn bit (cont0f: d3 ) = 0 and dspresetn bit (cont0f: d2) = 0 ). write 0 into the 0 registers. do not write data into cont2b C cont2f . [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 52 - v power - up sequence 1. when not downloading settings and programs from eeprom the ak77 55 should be powered up when the pdn pin 3 / avdd and tvdd must be powered up first before dvdd when dvdd is supplied externally (ldoe pin = 3 l ). in this case, the power - up sequence between avdd and tvdd is not critical. control register settings are initialized by the pdn pin = 3 l . set the 3 ' 1 s l q w r 3 + w r v w d u w w k h s r z h u v x s s o \ f l u f x l w v i r u 5 ( ) analog reference voltage source) generator and digital circuits (only when ldoe pin = 3 h ) after all power supplies are fed. control register access must be made after 1ms from the pdn pin = 3 h . s et aine bit (co nt00 : d3 ) to 3 1 fist when using the in1/inp1, in2/inn1, in3/inp2 and in4/inn2 pins as analog inputs. the pll starts operation by a clock res e t release (ckreset n bit (cont01: d0) 3 : 3 d q g generates the internal master clock after se tting control registers. therefore, necessar y system clock must be input and control register settings for cont00 ~ cont01 are must be finished before releasing the clock reset. interfacing with the ak77 55 except control register settings should be made w hen pll oscillation is v w d e l o l ] h g d i w h u f o r f n u h v h w u h o h d v h w d n h d p v l q w h u y d o r u f r q i l u p 3 + level output of plllock signal from the sto/rdy pin) ( figure 24 ) . however, dsp program and coefficient data can be wr itten even when the system clock is stopped. dsp programs and coefficient data can be written in 1ms by setting dlrdy bit = 3 : 3 & 2 1 7 ) ' ). dlrdy bit (cont0f: d0) p x v w e h v h w w r 3 d i w h u w k h g r z q o r d g ( figure 25 ). when using a crystal oscillator in master mode, set the ckm[2:0] bits (cont00: d6 - d4) = 0h or 1h, and release the clock reset after crystal oscillation is stabilized. the stabilizing time of cry stal oscillation is dependent on the crystal and exter nal circuits. the system clock must not be stopped except during the clock reset and power - down mode. figure 24 . power - up sequence 1 ( when not downloading from eeprom ) ( w ith external power supply (ldo e pin = 3 l ), no downloading from eeprom) dsp p rogram tvdd,avdd p d n (p in) cresetn bit(reg.) power off before pll stable oscillation access is not permitted (10ms) command code and dsp p rogram download no time limitation internal pllclk ( internal master clock ) x ti,bick (p in) ckresetn bit (reg.) 1 m s(min) cont reg. setting 6 00 n s (min) clock stabilizataion si ( spi ),sda( i2c ) dspresetn bit(reg.) dvdd [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 53 - figure 25 . power - up sequence 2 ( w ith external power supply (ldoe pin = l ), dlrdy setting, no downloading from eeprom ) 2. when downloading settings and pro grams from eeprom when downloading programs from an eeprom , i 2 c interface (i2csel pin = h ) and a 12.288mhz clock input to the xti pin are necessary, or a 12.288mhz crystal oscillator must be connected to the xti and xto pins . in this case, only ckm mode 0 and 2 (cont00: d6 - d4) are available. the ak77 55 should be powered up when the pdn pin = l. avdd and tvdd must be powered up first before dvdd when dvdd is supplied externally (ldoe pin = l ). in this case, the power - up sequence between avdd and tvdd is not critical. set the pdn pin to h to start the power supply circuits for ref ( analog reference voltage source) generator and internal digital circuit (only when the ldoe pin = h ) after all power supplies are fed. there are three ways to start downl oading control register settings, dsp programs and coefficient ram: by pdn pin (1) ( figure 26 ) , by exteep pin (2) ( figure 26 ) and by dls bit (3) ( figure 27 ) . dlrdy =1 dsp program cont reg. setting dlrdy =0 tvdd, a vdd pdn( p in) power off before pll stable oscillation access is not permitted (10ms) internal pllclk xti ,bick(p in) ckresetn bit (reg.) 1ms(min) 600ns( min) clock stabilization s i(spi ) , sda(i2c) c resetn bit(reg ) 1ms(min) dspresetn bit(reg ) ( internal master clock ) dvdd [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 54 - figure 26 . power - up sequence 3 ( with external power supply (ldoe pin = l ), downloading from eeprom (1)(2)) (1) start downloading by pdn pin power on (avdd, tvdd) , i2csel pin = h , exteep pin= h (dvdd ), pdn pin= l h (2) start downloading exteep pin (dotted line) power on ( avdd, tvdd) , i2csel pin = h (dvdd ) , pdn pin = l h exteep pin = l h figure 27 . powe r - up sequence 4 ( with external power supply (ldoe pin = l ), downloading from eeprom (3)) (3) start downloading dls bit power on (avdd, tvdd) , i2csel pin= h (dvdd ) , pdn pin= l h dls bit = 0 1 tvdd, avdd p d n( p in) cresetn bit(reg.) power off x ti (p in) ckre setn bit (reg.) c ont reg. setting, dsp program 6 00 n s(min) clock stabilization (12.288mhz) sda (p in) dspresetn bit(reg.) i 2csel(p in) e xteep(p in) e est(p in) s to(p in) success e rror ( eeprom ak7755 ) (1) (2) 1ms(min) dvdd tvdd, avdd p d n( p in) cresetn bit(reg.) power off x ti (p in) ckresetn bit (reg.) 6 00 n s(min) clock stabilization (12.288mhz) dsprese tn bit(reg.) i 2csel(p in) e est(p in) s to(p in) success e rror (1) 1ms(min) c ont reg. setting, dsp program sda (pin) dls bit ( eeprom ak7755 ) (3) (up ak 7755 ) dl s=1 dvdd [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 55 - ldo (internal circuit drive regulator) the ak77 55 has a regulator for driving internal digital circuits (ldo). when using the ldo, the ldoe pin must be fixed to h and c onnect a 1 f (30%) capacitor between the avdrv pin and the vss pin. the ldo starts operation by releasing power - down mode, and control register write/read can be made 1ms after the power - down release. the ak77 55 has an overcurrent protection circuit to avoid abnormal heat of the device that is caused by a short of the avdrv pin to vss and etc. , and an overvoltage protection circuit to pr otect from exceeded voltage when the voltage to the avdrv pin gets too high. when these protection circuits perform, internal circuits are powered down and the sto pin outputs l. the internal circuit will not return to a normal operation until being rese t by the pdn pin after removing the problems. figure 28 . power - up sequence 5 ( with ldo (ldoe pin = h ) , no downloading from eeprom) power - down sequence the ak77 55 should be powered down when the pdn pin = l. stop external clocks during this power - down state and then off the power supplies. do not input external clocks when the power supplies are off ( a current will flow through protection diode s). avdd and tvdd must be powered down after dvdd wh en dvdd is supplied externally (ldoe pin = l ). in this case, t he power - down sequence between avdd and tvdd is not critical. figure 29 . power - down sequence dsp program tvdd,avdd p d n (p in) cresetn bit(reg.) power off before pll stable oscillation access is not permitted (10ms) command code and dsp p rogram download no time limitation internal pllclk ( internal master clock ) x ti,bick (p in) ckresetn bit (reg.) 1 m s(min) cont reg. setting 6 00 n s (min) clock sta bilization si ( spi ),sda( i2c ) dspresetn bit(reg.) avdrv (pin) ldoe (pin) sto (pin) t vdd, a vdd pd n(pin) power off dvdd [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 56 - power - down and reset 1. power - down, reset and power management of the ak7755 the ak77 55 has four types of power - down and reset function s that are power - down ( pdn pin), clock reset (c l kr e s e tn bit (cont01:d0) ), codec reset (cr e s e tn bit (cont0f:d3) ) and ds p reset (dspr e s e tn bit (cont0f:d2) ). each block can be powered - down by power management registers. 2. power - down the ak7755 is powered down by setting the pdn pin = l . the pdn pin must be set to l when power up the ak7755. the statuses of output pin s in power - down mode are shown below. ldoe pin = l (external 1.2v supply mode) no pin name i/o power - down mode status no p in name i/o power - down mode status 1 vcom o l 1 7 so /sda i/o hi - z 6 sto/rdy o h 18 s clk/scl i/o hi - z 7 lrck i/o l 2 6 out3 o hi - z 8 bick i/o l 2 7 out2 o hi - z 9 clko o l 2 8 out1 o hi - z 1 0 xto o h 31 in4/inn2/dmclk2 i/o hi - z 11 xti i h 32 in3/inp2/dmdat2 i hi - z 1 4 jx2/ sdout3 /jx2/mat1 i/ o l 33 in2/inn1/dmclk1 i/o hi - z 1 5 sdout 2/jx3/mat1 i/ o l 34 in1/inp1/dmdat1 i hi - z 16 sdout 1 o l note 44 . [i/o] indicates input / output attribute of each pin. ldoe pin = h ( ldo mode ) no pin name i/o power - down mode status no pin name i/o power - down mode status 1 vcom o l 1 7 so /sda i/o hi - z 6 sto/rdy o l 18 s clk/sc l i/o hi - z 7 lrck i/o l 24 avdrv o l 8 bick i/o l 2 6 out3 o hi - z 9 clko o l 2 7 out2 o hi - z 1 0 xto o h 2 8 out1 o hi - z 1 1 xt i i h 31 in4/inn2/dmclk2 i/o hi - z 1 4 jx2/ sdout3 /jx2/mat1 i/ o l 32 in3/inp2/dmdat2 i hi - z 1 5 sdout 2/jx3/mat1 i/ o l 33 in2/inn1/d mclk1 i/o hi - z 16 sdout 1 o l 34 in1/inp1/dmdat1 i hi - z 3. power - down release 3 - 1. ldoe = l (external 1.2v supply mode) dvdd, tvdd and avdd should be supplied when the pdn pin = l . by bringing the pdn pin h 6 00 n s (min) after all power supplies are fed (dvdd, t vdd and a vdd), ref voltage circuit (analog reference voltage) starts operat ion . control register write / read should be made 1ms after bringing the pdn pin = h ( figure 24 ). avdd and tvdd must be powe red up first before dvdd. in this case, the power - up sequence between avdd and tvdd is not critical. 3 - 2 . ldoe = h ( ldo mode) tvdd and avdd should be supplied when the pdn pin = l . by bringing the pdn pin h 6 00 n s (min) after tvdd and avdd are fed , t he power supply circuits for ref generator and internal digital circuit start operat ion . control register write / read should be made 1ms after bringing the pdn pin = h ( figure 28 ). [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 57 - 4 . clock reset clock reset i s defined as when ckresern bit (cont 01: d 0 ) = 0 after p ower - down release (pdn pin = h ) . the ak7755 is in the clock reset state after rele asing power - down . at this time, all internal block s of the ak7755, except the ref circuit and the power supply circ uit for digital block , are in power - down mode. even the pll for internal master clock generation is not in operation. control register write/read should be made 1ms (min.) after power - down release. clock generating control registers (cont00 ~ cont01) mus t be set during clock reset. aine bit (cont0 0 : d3 ) should be set to 1 first when using the in1/inp1, in2/inn1, in3/inp2 and in4/inn2 pins as analog inputs. dsp pr ogr am and coefficient ram data writing to the dsp become available in 1ms by setting dlrdy b i t (cont0f: d0) = 0 1 during clock reset (ckresetn bit = 0 ). dlrdy bit must be set to 0 when finishing downloading . n ecessary system clock (xti@ckm mode0 - 2 or bick@ckm mode 3, 5 (cont00: d6 - d4) ) must be input before releasing the clock reset ( figure 16 ) . the pll for internal master clock starts operation and generating master clock when the clock reset state is released (ckr e s e t n bit = 1). do not send dsp programs, coefficient data or a command code for s ystem reset release from a microcontroller to the ak7755 until the pll oscillation is stabilized (for 10ms or during low output period of the plllock signal from the sto pin ). system clocks must be changed during a clock reset or in power - down mode (pdn pin = l). the ak77 55 enters clock reset state by setting ckresetn bit to 0 after system reset. the pll and the internal clock are stopped by this clock reset and the clock change can be done safely. change register settings and system clock frequencies during the clock reset. after a system c l ock is stabilized, the pll starts operation by setting ckresetn bit to 1. figure 30 . cl o c k reset sequence ( e.g. ckm mode0 ckm mode 3 ) cs n sclk (simplified) si 0xc f 0x0 0 0xc f 0x 0c command code & dsp program transmitting period 0xc 1 0x0 0 ckr e s e t n input clock changeable period 0xc 1 0x0 1 pll stable oscillation xti b ick ckm mode0 ckm mode 3 c reset n / dspreset n 0xc 0 0x3x [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 58 - 5 . system reset system reset is defined as when cresetn bi t (cont0f: d3) = 0 and dspr e s e tn bit (cont0 f: d 2 ) = 0 after clock reset is released ( ckresetn bit (cont01 : d0) = 1 ). pram and cram downloading should be executed in this state. pram and cram accessing of the ak7755 should be made when pll oscillation is stabilized after clock reset release (take a 10ms interval or confirm h level output of plllock signal from the sto pin) . system reset is released when either codec reset (cresetn bit) or dsp reset (dspresetn bit) is released ( 0 1 ) after dsp programs and coefficient data are transmitted . then the ak7755 starts generating necessary clocks for adc, dac and dsp operations . a system reset image is shown below. figure 31 . system reset structure in slave mode, t he ak7755 starts operation in synchronization of a n lrck rising edge (falling edge in i 2 s mode ) when system reset is released. i f the lrck is stopped or the lrck phase is shifted more than 1/4fs, the ak7755 becomes the sys tem reset state automatically. in this case, the system reset state is released if the lrck is input again. ram clear the ak77 55 has a ram clear function. after system reset release (during run), data ram and delay ram are cleared by 0 (ram clear). the internal pll must have a stable oscillation before system reset release . the required time to clear ram is 400s. in the ram clear sequence, it is possible to send commands to the dsp. (dsp is stopped during ram clear sequence. the sent command is accepted automatically after this sequence is completed.) figure 32 . ram clear sequence dspresetn bit s resetn cresetn bit pdn ( p in) dspreset n bit ram clear period dsp program operation start ram clear dsp start [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 59 - serial data interface serial audio data pins; the sdin1, sdin2, sdout1, sdout2 and sdout3 pins are interfaced with an external system by lrck and bick. control register settings are needed to us e these interfaces (refer to block diagram ( figure 1 ) and control register setting ). the data format is 2's compliment msb first. i/o format supports msb justified, lsb justified , i 2 s compatible and pcm format . (in i 2 s compatible /pcm mode, all audio data in put and outpu t pins are in i 2 s compatible/pcm format , respectively .) the input ( s din1 and sdin2 ) format is 24 - bit msb justified at default. 24 - bit/20 - bit/16 - bit lsb justified , i 2 s and pcm formats are also selectable by control register dif[1 :0] bits . the output ( s dou t1 , adout2 and sdout3 ) format is 24 - bit msb justified at default. 2 4 - bit/20 - bit/16 - bit lsb justified , i 2 s and pcm formats are selectable by setting dof[1:0] bits. the sdout1 also supports 8 - bit msb justified - law and 8 - bit msb justifid a - law formats. the output data of the adc (sdoutad and sdoutad 2 ) is fixed to 24 - bit msb justified. mode lrif[1:0] difdif2, difda[1:0] or dof2, 3, 4[1:0] dif1[2:0] or dof1[2:0] bitfs[1:0] format 0 000h 000h 0h 0h msb 24 - bit 64fs 1 000h 011h 1h 0h/1h lsb 24 - bit 64fs/48fs 2 000h 102h 2h 0h/1h lsb 20 - bit 64fs/48fs 3 000h 113h 3h 0h/1h/2h lsb 16 - bit 64fs/48fs/32fs 4 0h n/a 4h 0h msb 8 - bit - law 5 0h n/a 5h 0h msb 8 - bit a - law 6 011h 000h 0h 0h i 2 s compatible 7 102h 000h 0h 0h/3h pcm short frame 64fs/256fs 8 113h 000h 0h 0h/3h pcm long frame 64fs/256fs serial data format examples 1. msb justified (mode 0) fig ure 33 . msb j ustified bick 64fs 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 left ch l rck b ick right ch m: msb, l: lsb 22 21 20 19 2 1 l m s dout1 , 2, 3 dof mode 0 22 21 20 19 2 1 l m m: msb, l: lsb 22 21 20 19 2 1 l m s din1, 2 dif mode 0 22 21 20 19 2 1 l m [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 60 - 2 . lsb justified ( mode 1, 2, 3) figure 34 . lsb j ustified bick 64fs figure 35 . lsb justified bick 48fs left ch right ch m:msb ,l:lsb s din1,2 dif mode 1 s din1,2 dif mode 3 sdout1 ,2,3 dof mode 1 s dout1,2,3 dof mode 2 l rck b ick s din1,2 dif mode 2 dont care 1 l 15 1 4 1 3 1 2 1 1 1 0 m 18 17 16 dont care 1 l 15 1 4 1 3 1 2 1 1 1 0 m 18 17 16 dont care 1 l m 1 4 1 3 1 2 1 1 1 0 dont care 1 l m 1 4 1 3 1 2 1 1 1 0 23 22 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 1 0 21 2 0 22 21 20 19 1 l m 18 17 16 15 14 1 3 1 2 1 1 1 0 23 22 19 18 17 16 1 5 1 4 1 3 1 2 1 1 1 0 1 0 21 2 0 22 21 20 19 1 l m 18 17 16 15 14 1 3 1 2 1 1 1 0 sdout1,2,3 dof mode 3 22 21 20 19 1 l m 18 17 16 15 14 1 3 1 2 1 1 1 0 22 21 20 19 1 l m 18 17 16 15 14 1 3 1 2 1 1 1 0 1 l 15 1 4 1 3 1 2 1 1 1 0 18 17 16 msb 1 l 1 4 1 3 1 2 1 1 1 0 msb 1 l 15 1 4 1 3 1 2 1 1 1 0 18 17 16 msb 1 l 1 4 1 3 1 2 1 1 1 0 msb 31 30 23 22 21 20 19 18 17 16 15 14 1 0 31 30 1 0 23 22 21 20 19 18 17 16 15 14 left ch right ch m: msb, l: lsb s din1, 2 dif mode 1 22 21 20 19 dont care 1 l m 18 17 16 15 14 22 21 20 19 don t care 1 l m 18 17 16 15 14 dont care 1 l m 14 dont care 1 l m 14 dont care 1 l m 18 17 16 15 14 dont care 1 l m 18 17 16 15 14 s din1, 2 dif mode 2 s din1, 2 dif mode 3 sdout1 , 2, 3 dof mode 1 22 21 20 19 msb 1 l 18 17 16 15 14 22 21 20 19 msb 1 l 18 17 16 15 14 1 l 18 17 16 15 14 1 l 18 17 16 15 14 s dout1, 2, 3 dof mode 2 msb msb l rck b ick msb 1 l 14 msb 1 l 14 sdout 1, 2, 3 dof mode 3 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 61 - figure 36 . lsb justified bick 32fs 3. msb 8 - bit - law figure 37 . m sb justified 8 - bit - law, 8 - bit a - law bick 64fs 4 . i2s ( mode6 ) figure 38 . i2s bick 64fs left ch right ch s din1,2 dif mode 3 l rc k b ick sdout1,2,3 dof mode3 15 14 1 1 10 9 8 7 6 5 4 3 2 1 0 13 12 15 14 11 10 9 8 7 6 5 4 3 2 1 0 13 12 14 13 12 1 1 m 1 0 9 8 7 6 5 4 3 2 1 l 14 13 12 1 1 m 1 0 9 8 7 6 5 4 3 2 1 l 14 13 12 1 1 m 1 0 9 8 7 6 5 4 3 2 1 l 14 13 12 1 1 m 1 0 9 8 7 6 5 4 3 2 1 l 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0 left ch l rck b ick right ch m:msb,l:lsb 6 5 4 3 2 1 l m s dout1 dof mode4/5 6 5 4 3 2 1 l m m:msb,l:lsb 22 21 20 19 16 1 l m sdout 2,3 dof mode0 22 21 20 19 16 1 l m m:msb,l:lsb 6 5 4 3 l m s din1 dif mode 4 /5 6 5 4 3 l m m:msb,l:lsb 22 21 20 19 16 1 l m s din 2 dif mode0 22 21 20 19 16 1 l m 2 1 2 1 18 17 18 17 18 17 18 17 m: msb, l: lsb 22 21 20 3 2 1 l m s din1, 2 22 21 20 3 2 1 l m left ch 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 right ch 10 9 8 7 6 5 4 3 2 1 0 m: msb, l: lsb 22 21 20 3 2 1 l m s dout1, 2, 3 22 21 20 3 2 1 l m l rck b ick [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 62 - 5 . pcm short fra me ( mode7 ) figure 39 . 64fs pcm short frame figure 40 . pcm short frame 256fs 6 . pcm long frame (mode8 ) figure 41 . 64fs pcm long frame sf 63 m: m sb, l: lsb 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 s din1, 2 10 9 8 7 6 5 4 3 2 1 0 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m s dout1, 2, 3 tbclk 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m left ch right ch l rck b ick sf 255 m:msb,l:lsb 254 253 252 251 234 233 232 231 230 229 228 227 226 225 224 223 222 2 21 2 20 219 s din1,2 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m 202 201 200 199 198 3 2 1 0 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m s dout1,2,3 tbclk left ch right ch l rck b ick tbclk 32 tbclk 2 56 lf 63 m: msb, l: lsb 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 sdin1, 2 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m 10 9 8 7 6 5 4 3 2 1 0 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m sdout1, 2, 3 left ch right ch tbclk tbclk 32 tbclk t ts - tbclk tbclk 32 lrck bick [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 63 - figure 42 . pcm long frame 256fs 7. tdm mode tdm interface formats shown below are available by setting tdm 256 bit = 1 . bitfs[1:0] bits should be set to 3h sinc e bick is fixed to 256fs. m ode lrif[1:0] tdmmode[1:0] format note 0 0h 0h msb 24 - bit 1 0h 1h msb 24 - bit slot7 and 8 i nput s n ot a vailable 2 0h 2h msb 24 - bit slot5, 6, 7 and 8 inputs not a vailable 3 1h 0h i 2 s compatible 4 1h 1h i 2 s compatible slot 7 and 8 inputs not a vailable 5 1h 2h i 2 s compatible slot5, 6, 7 and 8 inputs not a vailable 6 2h 0h pcm short frame 7 2h 1h pcm short frame slot7 and 8 inputs not a vailable 8 2h 2h pcm short frame slot5, 6, 7 and 8 inputs not a vailable 9 3h 0h pcm lon g frame 10 3h 1h pcm long frame slot7 and 8 inputs not a vailable 11 3h 2h pcm long frame slot5, 6, 7 and 8 inputs not a vailable lf 255 m:msb,l:lsb 254 253 252 251 234 233 232 231 230 229 228 227 226 225 224 223 222 2 21 2 20 2 19 s din1, 2 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m 202 201 200 199 198 4 3 2 1 0 22 21 20 19 2 1 l m 22 21 20 19 2 1 l m s dout1, 2, 3 left ch right ch tbclk tbclk 32 l rck b ick tbclk 256 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 64 - figure 43 . tdm mode msb justified 24 - bit (internal signals are indic ated by dotted lines) figure 44 . tdm mode i 2 s compatible (internal signals are indicated by dotted lines) bick(256fs) sd out 1 sd in 1 (tdm mode0) d out 1l 32 bick din1 l din1 r din 2 l din 2 r d out1 r lrck ( slave ) sd in2 dout 2l dout2 r (don t care) dout3 l dout3 r l rck( master ) 256bick dout 4l dout 4 r 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4 s lot5 s lot6 s lot7 s lot8 d in3 l d in3 r din 4 l din 4 r sdin1(tdm mode 1 ) sdin1(tdm mode 2 ) din1l din1r din2l din2r sdoutad l ch sdoutad r ch sdoutad 2 lch 22 0 22 0 22 23 23 23 22 0 22 0 23 23 22 0 2 2 0 23 23 22 0 22 0 23 23 22 0 22 0 22 23 23 23 22 0 22 0 23 23 22 0 22 0 23 23 22 0 22 0 23 23 din1l din1r din2l din2r d in3 l d in3 r sdoutad l ch sd outad r ch 22 0 22 0 23 23 22 0 22 0 23 23 22 0 22 0 23 23 22 23 22 23 22 0 22 0 23 23 22 0 22 0 23 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 sdoutad2 r ch 22 0 23 bick(256fs) sd out 1 sd in 1 (tdm mode 3 ) 2 3 0 d out 1l 32 bick din 1 l din1 r din 2 l din 2 r 2 3 0 d out1 r 2 3 lrck ( slave ) sd in2 2 3 0 dout 2l 2 3 0 dout2 r (don t care) 2 3 0 dout3 l 2 3 0 dout3 r l rck( master ) 256bick 23 0 23 0 dout 4l dout 4 r 23 0 23 0 23 23 0 23 0 23 0 23 0 23 0 23 0 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4 s lot5 s lot6 s lot7 s lot8 d in3 l d in3 r din 4 l din 4 r sdin1(tdm mode 4 ) din1l din1r din2l din2r 23 0 23 0 23 23 0 23 0 23 0 23 0 23 0 23 0 d in3 l d in3 r sdoutad l ch sdoutad r ch sdin1(tdm mode 5 ) din1l din1r din2l din2r 23 0 23 0 23 23 0 23 0 23 0 23 0 sdoutad l ch s doutad r ch 23 0 sdoutad 2 lch 23 0 sdoutad2 r ch [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 65 - figure 45 . tdm mode pcm short frame (inte rnal signals are indicated by dotted lines) figure 46 . tdm mode pcm long frame (internal signals are indicated by dotted lines) bick(256fs) sd out 1 sd in 1 (tdm mode 6 ) 2 3 0 d out 1l 32 bick din1 l din1 r din 2 l din 2 r 2 3 0 d out1 r 2 3 lrck sd in2 2 3 0 dout 2l 2 3 0 dout2 r (don t care) 2 3 0 dout3 l 2 3 0 dout3 r 256bick 23 0 23 0 dout 4l dout 4 r 23 0 23 0 23 23 0 23 0 23 0 23 0 23 0 23 0 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4 s lot5 s lot6 s lot7 s lot8 d in3 l d in3 r din 4 l din 4 r sdin1(tdm mode 7 ) din1l din1r din2l din2r 23 0 23 0 23 23 0 23 0 23 0 23 0 23 0 23 0 d in3 l d in3 r sdoutad l ch sdoutad r ch sdin1(tdm mode 8 ) din1l din1r din2l din2r 23 0 23 0 23 23 0 23 0 23 0 23 0 sdoutad l ch sdoutad r ch 23 0 sdoutad 2 lch 23 0 sdoutad2 rch bick(256fs) sd out 1 sd in 1 (tdm mode 9 ) d out 1l 32 bick din1 l din1 r din 2 l din 2 r d out1 r lrck sd in2 dout 2l dout2 r (don t care) dout3 l dout3 r 256bick dout 4l dout 4 r 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick 32 bick s lot1 s lot2 s lot3 s lot4 s lot5 s lot6 s lot7 s lot8 d in3 l d in3 r din 4 l din 4 r sdin1(tdm mode 1 0 ) sdin1(tdm mode 11 ) din1l din1r din2l din2r sdoutad l ch sdoutad r ch sdoutad 2 lch 22 0 22 0 22 23 23 23 22 0 22 0 23 23 22 0 2 2 0 23 23 22 0 22 0 23 23 22 0 22 0 22 23 23 23 22 0 22 0 23 23 22 0 22 0 23 23 22 0 22 0 23 23 din1l din1r din2l din2r d in3 l d in3 r sdoutad l ch sd outad r ch 22 0 22 0 23 23 22 0 22 0 23 23 22 0 22 0 23 23 22 23 22 23 22 0 22 0 23 23 22 0 22 0 23 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 sdoutad2 r ch 22 0 23 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 66 - p interface setting and pin status spi or i 2 c bus interface mode can be selected by the i2csel pin . pin statuses that are changed by i2csel pin setting are shown below. i2csel pdn so/sda s clk /s cl spi interface l l hi - z (csn pin = 2 c bus h l hi z hi z h when not interfacing to a micro controller or the ak7755 is in power - down mode in spi interface mode. spi interface (i2csel pin = l) 1. co nfiguration the access format is: command code (8bit s ) + address + data ( msb first ). bit length command c ode 8 msb bit is r/w flag. the following 7 - bits indicate access area such as pram/ cram/registers. address 16 or 0 valid only for those cases wher e accessed areas have addresses such as pram /cram/ofreg. when no address is assigned, there is no data. data later section write or read data sopcfg bit selects so output (hi - z or low) during csn = h . ? w rite operation figure 47 . spi interface write ? read operation figure 48 . spi interface read cs n sclk si command code (8bit) address (16bit or 0bit) data (write) so dont care (l/h) x (l/h) hi - z hi - z echo back low low cs n sclk si command code (8bit) address (16bit or 0bit) so data (read) dont care (l/h) x (l/h) hi - z hi - z echo back low low [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 67 - 2. c o mmand code bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w flag area to be accessed accompanying data to the access area r/w flag : write at 1, read at 0. access data and accompanying data bit6 bit5 bit4 bit3~0 0 0 0 number of write write preparation to cram during run 0 0 1 number of write write preparation to ofreg during run 0 1 0 0100 0010 write operation to cram during run write operation to ofreg during run 0 1 1 1000 write /read operation to pram during system reset 0100 write /read operation to c ram during system reset 0010 write /read operation to o f reg during system reset 1011 wr ite /read operation to ac ram (accelerator coefficient ram) during system reset 1 0 0 register address internal control registers 00h ~ 0 fh 1 0 1 register address internal control registers 1 0h~1fh 1 1 0 0000 0110 1010 device identification (read only) inte rnal control registers 26 h internal control registers 2a h 1 1 1 0000 error status read 0010 crc write/read 0100 write operation of jx code 0110 read operation from mir1 1000 read operation from mir 2 1010 read operation from mir 3 11 00 read operation from mir 4 3. address the address description is always lsb justified. accessing command code bit[6:4]= 000 to 011 requires a 16 - bit address. accessing command code bit[6:4]= 100 to 111 requires no address. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 68 - 4. data the leng th of write data depends on the write area size. when accessing ram, data may be written to sequential address loc a tions by writing data continuously. write command address data length description 0x80~0x8f 16bit 24bitn write preparation to cram during run . command code bit3~bit0 bits determines the amount of write operation. ( 0x80 # of write: 1, 0x81 # of write: 2, ---- , 0x8f # of write: 16 ) if the actual amount of write operations exceeds the defined amount, that data will be ignored. 0x90~0x9f 16bit 24bitn write preparation to ofreg during run command code bit3~bit0 bits determines the amount of write operation. ( 0x90 # of write: 1, 0x91 # of write: 2, ---- , 0x9f # of write: 16 ) if the actual amount of write operations exceeds the defined amount, th at data will be ignored. 0xa2 16bit none write operation to ofreg during run. 0 address should be written. 0xa4 16bit none write operation to cram during run. 0 address should be written. 0xb2 16bit 24bitn write operation to ofreg during system reset 0xb4 16bit 24bitn write operation to cram during system reset 0xb8 16bit 40bitn write operation to pram during system reset 0xbb 16bit 24bitn write operation to acram during system reset 0xc0~0xdf none 8bit write operation to control registers 00 ~ 1fh 0x e6 none 8bit write operation to control register 26h 0x ea none 8bit write operation to control register 2ah 0xf2 none 16bit crc write 0xf4 none 8bit write operation of external conditional jump code data length is defined by the command code which specifies the area to be accessed. when accessing ram, data may be read from sequential address loc a tions by reading data continuously. writing other than this command code is prohibited. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 69 - read command address data length description 0x24 16bit 24bitn c ram/ofreg p reparation d ata read during run 0x32 16bit 24bitn read operation form ofreg during system reset 0x34 16bit 24bitn read operation from cram during system reset 0x38 16bit 40bitn read operation from pram during system reset 0x3b 16bit 24bit n read operation from ac ram during system reset 0x40~0x5f none 8bit write operation to control registers 00 ~ 1fh 0x60 none 8bit device identification 0x 66 none 8bit write operation to control register 26h 0x 6a none 8bit write operation to control regis ter 2ah 0x70 none 8bit dsp error status read 0x72 none 16bit crc result read 0x76 none 32bit read operation from mir1 28 - bit is upper - bit justified. lower 4 - bits are for validity flags. 0x78 none 32bit read operation from mir2 28 - bit is upper - bit justi fied. lower 4 - bits are for validity flags. 0x7a none 32bit read operation from mir3 28 - bit is upper - bit justified. lower 4 - bits are for validity flags. 0x7c none 32bit read operation from mir4 28 - bit is upper - bit justified. lower 4 - bits are for validity flags. reading other than this command code is prohibited. 5. echo - back mode the ak7755 has a n echo - back mode that the device outputs write data sequentially from the so pin. 5 - 1. write sequence figure 49 . echo - back writing 1 (spi) the input data of the si pin is echoed back on the so pin by shifting 8 - bit to the right. figure 50 . echo - back writing 2 (spi) it is possible to verify the written data by inputting an extra 8 - bit clock. if the dummy data is more than the data length, this dummy data is written on the next address. (40 bits for pram, 24 bits for cram and 24 bits for ofreg writings) cs n si command address1 address2 data1 data2 command address1 so command address1 address2 data1 command dontcare (l/h) hi - z or low cs n si 0xb4 0x00 0x00 data1 datan dummy 8bit so command address1 address2 data1 datan x (hi - z or low) x (hi - z or low) n=3~5 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 70 - 5 - 2. read sequence 1 (with pram, cram, ofreg addresses) figure 51 . read sequence1 in echo - back mode (spi) data of the address2 field is not echoed back in read operation. the read data on the so pin is output after writing to the address2 field. 5 - 3 . read s equence 2 ( no register address figure 52 . read sequence2 in echo back mode (spi) data output has priority in read sequence. 6. format 6 - 1. write operation during system reset 1 . program ram (pram) write (during system reset) fie ld write data (1) command code 0xb8 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (4) data1 0 0 0 0 d35 d34 d33 d32 (5) data2 d31~d24 (6) data3 d23~d16 (7) data4 d15~d8 (8) data5 d7~d0 five bytes of data may be written continuously fo r each address. 2. coefficient ram (cram) write (during system reset) field write data (1) command code 0xb4 (2) address1 0 0 0 0 0 a10 a9 a8 (3) address2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. cs n si command address1 address2 command address1 so command address1 read data read data command dontcare (l/h) hi - z or low cs n si command command so read data dontcare (l/h) hi - z or low dontcare (l/h) read data hi - z or low [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 71 - 3. offset reg (ofreg) write (during system reset) field write data (1) command code 0xb2 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 a5 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 0 0 0 d 12 d11 d10 d9 d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. 4. accelerator coefficient ram ( a cram) write (during system reset) field write data (1) command code 0xbb (2) address1 0 0 0 0 0 a10 a9 a8 (3) addr ess2 a7 a6 a5 a4 a3 a2 a1 a0 (4) data1 d19~d12 (5) data2 d11~d4 (6) data3 d3~d0 0 0 0 0 three bytes of data may be written continuously for each address. 6 - 2. write operation during system reset / run 1. control register write (during system reset / run) field write data (1) command code 0xc0~0xd f , 0xe6, 0xea (2) data d7~d0 2. external conditional jump code write (during system reset / run) field write data (1) command code 0xf4 (2) data d7~d0 3. crc code write (during system reset / run) fi eld write data (1) command code 0xf2 (2) data d15~d8 (3) data d7~d0 6 - 3. write operation during run 1. coefficient ram (cram) write preparation (during run) preparation write data (1) command code 0x80~0x8f (one data at 80h, sixteen data at 8fh) (2) address1 0 0 0 0 0 a10 a9 a8 (3) address2 a7 ~ a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 72 - 2. coefficient ram (cram) write operation (run) execute write data (1) command code 0xa4 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 note 46 . the command determines the length of the data. if the written data exceeds the allotted amount, the excess data is ignored. 3. offset reg (ofreg) write preparation (during run) preparation write data (1) command cod e 0x90 ~ 0x9f (one data at 0x90, sixteen data at 0x9f) (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 0 0 0 d12 d11 d10 d9 d8 (6) data3 d7~d0 4. offset reg (ofreg) write operation (during run) execu te write data (1) command code 0xa2 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 note 47 . the command determines the length of the data. if the written data exceeds the allotted amount, the excess data is ignored. 6 - 4. read operation during system reset 1. program ram (pram) read (during system reset) field write data readout data (1) command code 0x38 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 0 0 0 0 0 (4) data1 0 0 0 0 d35 d34 d33 d32 (5) data2 d31 ~d24 (6) data3 d23~d16 (7) data4 d15~d8 (8) data5 d7~d0 five bytes of data may be written continuously for each address. 2. coefficient ram (cram) read (during system reset) field write data readout data (1) command code 0x34 (2) address1 0 0 0 0 0 a10 a9 a8 (3) address2 a7 ~ a0 (4) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 73 - 3. offset reg (ofreg) read (during system reset) field write data readout data (1) c ommand code 0x32 (2) address1 0 0 0 0 0 0 0 0 (3) address2 0 0 0 a4 a3 a2 a1 a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 d15~d8 (6) data3 d7~d0 three bytes of data may be written continuously for each address. 4. accelerator coefficient ram (cr am) read (during system reset) field write data readout data (1) command code 0x3b (2) address1 0 0 0 0 0 a10 a9 a8 (3) address2 a7 ~ a0 (4) data1 d19~d12 (5) data2 d11~d4 (6) data3 d3~d0 0 0 0 0 three bytes of data may be written continuou sly for each address. 6 - 5. read operation during system rest / run 1. control register read (during system reset / run) field write data readout data (1) command code 0x40~0x5f , 0x66, 0x6a (2) data d7~d0 2. device identification (during system rest / run) field write data readout data (1) command code 0x60 (2) data d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 0 1 5 5 3. crc result reading (during system reset / run) field write data readout data (1) command code 0x72 (2) data1 d15~d8 (3) data2 d7~d0 4. dsp error status read (during system reset / run) field write data output (1) command code 0x70 (2) data active low output d7: crcerr n: 0: crc error d6: wdterr n : 0: watch dog timer error d5: gp0 0:clear 1: set d4: gp1 0:clear 1: set d3: plllock 0:unlock 1:lock d2: n/a d1: n/a d0: n/a [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 74 - 6 - 6. read operation during run 1. cram write preparation read (during run) field write data readout data (1) command code 0x24 (2) address1 a15~a8 (3) address2 a8~a0 (4 ) data1 d23~d16 (5) data2 d15~d8 (6) data3 d7~d0 2. ofreg write preparation read (during run) field write data readout data (1) command code 0x24 (2) address1 a15~a8 (3) address2 a8~a0 (4) data1 0 0 0 0 0 0 0 0 (5) data2 d15~d8 (6) data3 d7~d0 3. mir1/2/3/4 read (during run) field write data readout data (1) command code 0x76(mir1) 0x78(mir2) 0x7a(mir3) 0x7c(mir4) (2) data1 d27~d20 (3) data2 d19~d12 (4) data3 d11~d4 (5) data4 d3 d2 d1 d0 (flag3) (flag2) (flag1) (flag0) no te 48 . data is valid only when all flags are zero. 7. timing 7 - 1. ram writing timing during system reset write to program ram (pram), coefficient ram (cram), offset reg (ofreg) and accelerator coefficient ram (cram) during system reset in the order of command code, address and data. the pram start address is fixed to 0h. when writing the data to consecutive address locations, continue to input data only. pram address is incremented by 1 automatically. f igure 53 . writing to ram at consecutive address locations (spi) cs n si sclk dsp reset n bit rdy = h command address data data data data data dont care (l/h) dont care (l/h) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 75 - figure 54 . writing to ram at random address locations (spi) 7 - 2. ram writing timing during run these operations are to rewrite the coefficient ram (cram) and offset reg (ofreg) during run. data writing is executed in two steps; write preparation and write execution. the written data can be confirmed by reading the write preparation data. 1. write preparation after inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the starting address of write (16 bits all 0) and the number of data assigned by command code in this order. in slave mode, a write preparation command is proh ibited for 2 lrck cycles (2/fs) after releasing dsp reset (dspresetn bit). 2. write preparation data confirmation after write preparation, prepared data for writing can be confirmed. address and data are read in this order by write preparation data conf irmation command 24h. the data will be 0x000001 when reading more than write preparation data. execute write preparation again when the address and data are disturbed by external noise. 3. write execution upon completion of this operation, execute a r am write during run by inputting the correspon d ing command code and address (16 bits, all 0) in this order. note 49 . execute w rite preparation , write preparation read and write execution in this order . when writing to ram without a write preparation sequence, a malfunction occurs. access operation by a microcontroller is prohibited until rdy changes to h. write modification of the ram content is executed whenever the ram address for modification is assigned. for example, when 5 d ata are written, from ram address 10, it is ex e cuted as shown below. ram execution address 7 8 9 10 11 13 16 11 12 13 14 15 address 13 is not executed until rewriting address 12. cs n si sclk rdy = h command address data command address data dont care (l/h) dont care (l/h) dont care (l/h) dsp reset n bit [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 76 - figure 55 . cram/ofreg write preparation (spi) figure 56 . cram/ofreg write preparation confirm (spi) figure 57 . cram/ofreg write (spi) note 51 . if the dsp program is designed to refer all coefficients which may be changed by an external microcontroller, rdy signal rises to high within 2lrck after a writing command. no further access to dsp is permitted until this write operation is completed. however, while the csn pin is l l evel, rdy signal keeps l level. csn si sclk command c ode address rdy = h data 0 ( ex. ) when # of data is 4 cram 0x80( # of data: 1 ) ~ 0x8f( # of data: 16 ) ofreg 0x90( # of data: 1 ) ~ 0x9f( # of data: 16 ) cram command code 0x83 of reg command code 0x93 dont care (l/h) data 1 data n - 1 data n dont care (l/h) dsp reset n bit= 1 si sclk rdy= h 0x24 address data data data data data so dont care (l/h) dont care (l/h) cs n hi - z or low dsp rest n bit= 1 rdylg ( note 52 ) cs n si sclk dsp reset n bit= 1 command max 400ns rdy cram0xa4, ofreg0xa2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dontcare (l/h) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 77 - 7 - 3. exte r nal conditional jump external conditional jump code writing (during system reset and run) (1) command 0xf4 (2) data d7~d0 external conditional jump code can be input during both dsp reset and run. input d ata is set to the designated register on the rising edge of lrcko. the rdy pin changes to l when the command code is transferred, and it changes to h when write operations are completed. when any single bit of 1 data in 8 - bit external jump code match es an 1 bit data in the ifcon field, a jump instruction is executed. then, the rdy pin changes to h when the rise of lrcko is captured. access operation by microcontroller is prohibited until the rdy pin changes to h. ifcon field is the area where th e external conditions are written. this jump code is reset to 00h by setting the irstn pin to l, but it is not reset by system reset. 7 6 5 4 3 2 1 0 exte r nal conditional jump code check if 1 of ifcon field corresponds with external conditional jump including jump pins ? ? ? ? ? ? ? ? figure 58 . external conditional timing in s ystem r eset ( spi ) figure 59 . external conditional jump timing during run ( spi ) f4h d7d0 lrck cs n sclk dsp reset n bit si rdy dontcare (l/h) dontcare (l/h) next command write is available f4h d7 d0 cs n si sclk dsp reset n bit rdy lrc k dontcare (l/h) dontcare (l/h) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 78 - 7 - 4. ram reading timing during s ystem reset read program ram (pram), coefficient ram (cram), offset reg (ofreg) and accelerator coefficient ram ( a cram) during system reset in the order of the input command code and the address. after writing the command, the data comes out from the so p in synchronous with falling edge of sclk. (the si pin input data is dont care) when reading data at consecutive address locations, continue to input sclk as is. figure 60 . ram reading at consecutive a ddress (spi) 7 - 5. ram reading timing during system reset and run write a command code, to r ead control register s , device identification code, crc resu lt and error status during run time or system reset state. after completing a command code write, the d ata comes out from the so pin synchronous with falling edge of sclk. (the si pin input data is dont care) figure 61 . am reading during system reset/run (spi) echo back output cs n si sclk dsprstn bit rdy = h command address data so dont care (l/h) dont care (l/h) hi - z or low cs n si sclk d spreset n bit rdy = h command address data data data data data so echo back output dont care (l/h) dont care (l/h) hi - z or low [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 79 - i 2 c bus interface (i2csel pin= h) a ccess to the ak77 55 registers and ram is controlled by an i2c bus. the ak77 55 supports fast - mode i 2 c - bus (max: 400khz) only. 1. data transfer in order to access any ic devices on the i 2 c bus, input a start condition first, followed by a single slave addr ess which includes the devices address. ic devices on the bus compare this slave address with their own addresses and the ic device which has an identical address with the slave address generates an acknowledgement. an ic device with the identical address then executes either a read or a write operation. after the command execution, input a stop condition. 1 - 1. data change change the data on the sda line while the scl line is l. the sda line condition must be stable and fixed while the clock is h. change the data line condition between h and l only when the clock signal on the scl line is l. change the sda line condition while the scl line is h only when the start condition or stop condition is input. figure 62 . data cha nge (i 2 c) 1 - 2. start condition and stop condition a start condition is generated by the transition of h to l on the sda line while the scl line is h. all i n structions are initiated by a start condition. a stop condition is generated by the transition o f l to h on the sda line while the scl line is h. all instructions end by a stop cond i tion. figure 63 . start condition and stop condition (i 2 c) scl sda data line stable : data valid change of data allowed scl sda stop condition start condition [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 80 - 1 - 3. repeated start condition when a start condition is received again instead o f a stop condition, the bus changes to a repeated start condition. a repeated start condition is functio n ally the same as a start condition. figure 64 . repeated start conditions (i 2 c) 1 - 4. acknowledge an external device that is se nding data to the ak77 55 releases the sda line (h) after receiving one byte of data. an external device that receives data from the ak77 55 then sets the sda line to l at the next clock. this operation is called acknowledgement, and it enables verific ation that the data transfer has been properly executed. the ak77 55 generates an acknowledgement upon receipt of a start condition and a slave address. for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a read instruction, succeeded by generation of an acknowledgement, the ak 77 55 releases the sda line after outputting data at the designated address, and it monitors the sda line condition. when the master side generates an acknowledgement without sending a stop condition, the ak 77 55 outputs data at the next address location. when no acknowledgement is generated, the ak 77 55 ends data output (not acknowledged). figure 65 . generation of acknowledgement (i 2 c) scl sda repeated start condition start condition scl fro m master acknowledge data output by transmitter data output by receiver 1 9 8 start condition clock pulse for acknowledge not acknowledge [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 81 - 1 - 5. the first byte the first byte, which includes the slave - address, is input after the start condition is set, and a target ic device that will be accessed on the bus is selected by the slave - address. the slave - address is configured with the upper 7 - bits. when the i2csel pin = h and the exteep pin = l , d ata of the upper 6 - bits is 00110 0 . the next 1 bit is the address bits that select the desired ic wh ich are set by the cad pin . the slave address will be 0011000 when the i2csel pin = h and the exteep pin = l . however, the cad pin should be set to l if the matsel pin = l to set the slave address to 0011000 when downloading from eeprom by dls bit even if the i2csel pin = h and the exteep pin = l . when the slave - address is inputted, an external device that has the identical d e vice address generates an acknowledgement and instructions are then executed. the 8 th bit of the first byte (lowest bit) is allocated as the r/w bit. when the r/w bit is 1, the read instruction is executed, and when it is 0, the write inst ruction is executed. note 52 . in this document, there is a case that describes a write slave - address assignment when both a d dress bits match and a slave - address at r/w bit = 0 is received. there is a case that describes read s lave - address assignment when both address bits matches and a slave - address at r/w bit = 1 is received. 0 0 1 1 0 0 cad r/w when i2csel pin = h and exteep pin = l 0 0 1 1 0 0 0 r/w when i2csel pin = h and exteep pin = h , or using dls bit figure 66 . first byte configuration (i 2 c) 1 - 6. the second and succeeding bytes the data format of the second and succeeding bytes of the ak77 55 transfer / receive serial data (command code, address and data in microcontroller interf ace format) on the i 2 c bus are all configured with a multiple of 8 - bits. when transferring or receiving those data on the i 2 c bus, they are divided into an 8 - bit data stream segment and they are transferred / received with the msb side data first with an a cknowledgement in - between. example ) when transferring / receiving a1b2c3 (hex) 24 - bit serial data in micr o processor interface format: figure 67 . division of data (i 2 c) note 53 . in this document, there i s a case that describes a write instruction command code which is received at the se c ond byte as write command. there is a case that describes a read instruction command code which is received at the second byte as read command. (1) microcontroller interface format (2) i 2 c format a1 b2 c3 a1 b2 c3 a a 24bit 8bit 8bit 8bit a acknowledge (1) ?????`?`?`?? (1)i 2 c ?`?? [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 82 - 2. write sequence in the ak77 55 , when a write - slave - address assignment is received at the first byte, the write command at the second byte and data at the third and succeeding bytes are received. at the data block, address and write data are received in a single - byte unit e ach in accordance with a command code. the number of write data bytes is fixed by the received command code. figure 68 . write sequence (i 2 c) 3. read sequence in the ak77 55 , when a write - slave - addre ss assignment is received at the first byte, the read command at the second byte and the data at the third and succeeding bytes are received. at the data block, the address is received in a single byte unit in accordance with a read command code. when the last address byte (or command code if no address assignment is specified) is received and an acknowledgement is transferred, the read command waits for the next restart condition. when a read slave - address assignment is received at the first byte, data is transferred at the second and succeeding bytes. the number of readable data bytes is fixed by the received read command. after reading the last byte, assure that a not acknowledged signal is received. if this not acknowledged signal is not received, the ak77 55 continues to send data regardless whether data is present or not, and since it d oes not release the bus, the stop condition cannot be properly received. figure 69 . read sequence (i 2 c) sda slave address s s t a r t r/w="0" a c k command code a c k data(n) a c k data(n+1) a c k a c k data(n+x) a c k p s t o p sda slave address s s t a r t r/w="0" a c k a c k a c k data(n) a c k data(n+x) a c k p s t o p command code s slave address r/w="1" data(n+1) a c k n a c k m a s t e r m a s t e r m a s t e r m a s t e r a c k data(n) r e s t a r t [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 83 - 4. acknowledgement polling the ak77 55 cannot receive instructions while the rdy pin (data write ready pin) is at low level. the maximum trans i tion time of the rdy pin from low level to high level is 2/fs (fs: sampling frequency) , but it is possible to confir m in a faster cycle that the rdy pin has become high by checking the ak77 55 internal condition, which is made by verifying the a c knowledgement. 4 - 1. generation of not acknowledged the ak77 55 does not accept command codes until the rdy pin is set to a high level, when a command is r e ceived to set the rdy pin to a low level. in order to confirm the rdy pin condition, a write slave - address a s signment should be sent after a start condition. if the rdy pin is then at a low level, acknowledgement is not generated at the succeeding clock (generation of not acknowledged). after sending not acknow l edged, the bus is released and all receiving data are ignored until the next start condition (behaves as if it r e ceived slave address of other device). 4 - 2. when read slave - address assignment is received without receiving r ead c ommand c ode data read in the ak77 55 can be made only in the previously documented read sequence. data cannot be read out without receiving a read command code. t he ak77 55 generates a not acknowledged when a read slave - address assignment is received without proper receipt of read command. 5. limitation in use of i 2 c interface the i2c interface does not support the following features. no operation in hs mode (max:3.4mhz). the a k77 55 supports fast mode (max:400khz). note 54 . do not turn off the power of the ak77 55 whenever the power supplies of other devices of the same system are turned on. the source of the pull - up of sda and scl of i 2 c bus must not exce ed the t vdd. (the diode exists for t vdd in the sda and scl pins.) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 84 - analog input block 1. microphone input selector either analog input or digital microphone interface can be chosen for t he ak7755 . set aine bit (cont00: d3) to 1 when using #31 - 34 pi ns as analog input pin s, and set dmic1 (cont1e: d7) or dmic2 bit (cont1e: d4) to 1 when using these pins as digital microphone interface. adc input signal s can be swi t ched by difl bit (cont09: d5), dif r bit (cont09: d7) , inl bit (cont09: d4) and int r bit (cont09: d6) for analog inputs . when difl bit = 0 and d i fr bit = 0 , input si g n als of in1, in2, in3 and in4 pins for m icrophone amplifiers can be selected by inl and inr bits. w hen difl bit = 1 and difr bit = 1 , a differential input is acceptable as input pins becomes inp1/inn1 pins an d in p2/inn2 pins . figure 70 . microphone input selector adc l ch microphone input selector adc r ch microphone input selector dif l bit in l bit adc l ch dif r b it in r bit adc r ch 0 0 in 1 (default) 0 0 in 3 (default) 0 1 in 2 0 1 in 4 1 x inp 1 /inn 1 1 x inp 2 /inn 2 (x : do not care) (x: do not care) in1 /in p1 /dmdat1 pin ak7755 mic - amp rch i n2 /in n1 /dmclk1 pin in 4 /in n2 /dmclk2 pin in 3 /in p2 /dmdat2 pin adc lch inl bit difl bit mic - amp lch adc rch inr bit difr bit [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 85 - 2. microphone input gain the ak7755 has a microphone gain amplifier. l and r channel gains can be set independently by mgnl[3:0] bits (cont12: d3 - d0) and mgnr[3:0] bits (cont12: d7 - d4) . input impedance is typ. 20k ? . this gain amplifier executes zero cross detection when changing the gain by setting miclzce bit (cont1a: d0) = 1 / micrzce bit (cont1a: d1) = 1 . zero cross detection is executed on l and r channels independently. timeout period of the zero cross detection is 16ms. when miclzce bit = 0 / micrzce bit = 0 , zero cross detection is not performed and the volume is changed imm ediately when register is written. when writing to mgnl3 - 0 /mgnr3 - 0 bits continually, take an interval of zero crossing timeout periods or more. if the mgnl3 - 0 /mgnr3 - 0 bits are changed before zero crossing, the volume of lch and rch may differ. when the v olume that is same as the present is set, the zero crossing counter is not reset and timeout according to the previous writing timing. zero crossing timeout when miclzce bit = 1 / micrzce bit = 1 , the lch/rch volume level are changed independently by zero crossing detection or zero crossing timeout. fs zero cross timeout period 48khz 16ms mode mgnl[ 3 ] mgnr[ 3 ] mgnl[2] mgnr[2] mgnl[1] mgnr[1] mgnl[0] mgnr[0] input gain 0 0 0 0 0 0db (d efault ) 1 0 0 0 1 2 db 2 0 0 1 0 4 db 3 0 0 1 1 6 db 4 0 1 0 0 8 db 5 0 1 0 1 10 db 6 0 1 1 0 12 db 7 0 1 1 1 14 db 8 1 0 0 0 16db 9 1 0 0 1 18db a 1 0 1 0 21db b 1 0 1 1 24db c 1 1 0 0 27db d 1 1 0 1 30db e 1 1 1 0 33db f 1 1 1 1 36db table 2 . microphone input gain 3. analog drc (adrc) the microphone input gain can be set by dsp program s with the ak7755 . this function is enabled by setting adrcre bit = 1 / adrcle bit = 1 (cont1a : d3 / d2). in this setting , control registers mgnl[3:0] and mdnr[3:0] bits (cont12) are not valid. by reading amgn l [3:0] (cont1b: d3 - d0) / amgn r [3:0] (cont1b: d7 - d4) bits, gain settings can be do w nloaded externally. when miclzce bit = 1 / micrzce bit = 1 , the lch/rch volume level are changed independently by zero crossing detection or zer o crossing timeout. please refer to the ak7755 programing manual for dsp programs. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 86 - 4. line input gain amplifier the ak7755 has a gain amplifier for line inputs . it is enabled by setting p mli bit (cont0f: d5) = 1 , and it outputs a signal to the l chann el of the adc2. lign[3:0] bits (cont13: d7 - d4) controls the gain. the typical input i mpedance is 20k ? (typ) . a p op noise occur s if the input gain is changed during operation. the ak7755 becomes digital microphone interface mode when dmic2 bit (cont1e: d4) = 1 . digital microphone i nput data to the dmdat2 pin is input to the lch/rch of the adc2. adc2 input setting d mic2 bit adc 2 l ch input adc 2 r ch input 0 lin no (default) 1 digital microphone digital microphone mode l ign [ 3 ] lign [2] lign [1] lign [0 ] input gain 0 0 0 0 0 0db (d efault ) 1 0 0 0 1 - 3 db 2 0 0 1 0 - 6 db 3 0 0 1 1 - 9 db 4 0 1 0 0 - 12 db 5 0 1 0 1 - 15 db 6 0 1 1 0 - 18 db 7 0 1 1 1 - 21 db 8 1 0 0 0 n/a 9 1 0 0 1 +3db a 1 0 1 0 +6db b 1 0 1 1 +9db c 1 1 0 0 +12db d 1 1 0 1 +15 db e 1 1 1 0 +18 db f 1 1 1 1 +21 db table 3 . line input gain [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 87 - adc block 1. adc high pass filter a digital high pass filter (hpf) is integrated for dc offset cancellation of the adc input . the cut - off frequency of the hp f is approximately 1hz (at fs=48khz). fs 48khz 44.1khz 8khz cut - off frequency 3.73 hz 3.43 hz 0. 62 hz 2. adc soft mute 2 - 1. description the adc block has a digital soft mute circuit. the soft mute operation is performed in the digital domain. the output s ignal is attenuat ed to - in adc digital volume level x att transition time from the current adc digital volume setting level by setting admute and ad2mute bit s to 1. when the ad mute (cont1a: d7) and ad 2mute (cont1a: d6) bi ts are returned to 0, the mute is cancelled and the output attenuation gradually changes to adc digital volume setting level in adc digital volume level x att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and r eturned to adc digital volume setting level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. the transition time from 0db to - and vice versa is 828 lrck cycles. the soft mute function works when the adc is in operation. the a ttenuation value is initialized by the pdn pin = l . figure 71 . adc s o ft mute 2 - 2. input select o r switching sequence the input selector shou ld be changed after soft muting to avoid the switching noise of the input selector. inp ut selector switching sequence 1. enable soft mute before changing the channel. 2. change the channel. 3. disable softer mute. figure 72 . adc input channel switching sequence example smute register value - db 0db attenuation output image group delay ( gd ) 828/fs 828/fs group delay ( gd) admute attenuation channel datt level - (1) (2) i n1/in3 in 2 /in 4 (1) (3) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 88 - the period of (1) varies by the setting value of datt bit. the transition time of attenuation amount from 0db to - and vice versa is shown below. atspad (1) period (max) lrck cycle fs=48khz fs=44.1 khz fs=8khz 0 828/fs 17.25ms 18.82ms 103.5ms 1 828/fs x 4 69ms 75.27ms 414ms when changing channels, the input channel should be changed during (2). the period of (2) should be around 200ms because there is some dc difference between the channels (3). 2 - 3. adc digital volume the adc of the ak7755 has channel - independent digital volume control (256 levels, 0.5db step). voladl [7:0 ] bits (cont15:d7 - d0), volad r [7:0 ] bits (cont16:d7 - d0), volad 2 l [7:0 ] bits (cont17:d7 - d0) and volad 2r [7:0 ] bits (cont1d: d7 - d0) control these volume values independently. adc stereo lch voladl [7:0] adc stereo rch voladr [7:0] adc 2 lch volad 2l [7:0] adc 2 rch volad 2r [7:0] attenuation level 00h 00h 00h 00h +24.0db 01h 01h 01h 01h +23.5db 02h 02h 02h 02h +23.0db : : : : : 2fh 2fh 2fh 2fh +0.5db 30h 30h 30h 30h 0.0db (d efault ) 31h 31h 31h 31h - 0.5db : : : : : fdh fdh fdh fdh - 102.5db feh feh feh feh - 103.0db ffh ffh ffh ffh mute ( - ) to l, the vola d l/r[7:0] bits are initialized to 30h. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 89 - code db code db code db code db code db code db code db code db 00h 24.0 20h 8.0 40h - 8.0 60h - 24.0 80h - 40.0 a0h - 56.0 c0h - 72.0 e0h - 88.0 01h 23.5 21h 7.5 41h - 8.5 61h - 24.5 81h - 40.5 a1h - 56.5 c1h - 72.5 e1h - 88.5 02h 23.0 22h 7.0 42h - 9.0 62h - 25.0 82h - 41.0 a2h - 57.0 c2h - 73.0 e2h - 89.0 03h 22.5 23h 6.5 43h - 9.5 63h - 25.5 83h - 41.5 a3h - 57.5 c3h - 73.5 e3h - 89.5 04h 22.0 24h 6.0 44h - 10.0 64h - 26.0 84h - 42.0 a4h - 58.0 c4h - 74.0 e4h - 90.0 05h 21.5 25h 5.5 45h - 10.5 65h - 26.5 85h - 42.5 a5h - 58.5 c5h - 74.5 e5h - 90.5 06h 21 .0 26h 5.0 46h - 11.0 66h - 27.0 86h - 43.0 a6h - 59.0 c6h - 75.0 e6h - 91.0 07h 20.5 27h 4.5 47h - 11.5 67h - 27.5 87h - 43.5 a7h - 59.5 c7h - 75.5 e7h - 91.5 08h 20.0 28h 4.0 48h - 12.0 68h - 28.0 88h - 44.0 a8h - 60.0 c8h - 76.0 e8h - 92.0 09h 19.5 29h 3.5 49h - 12.5 6 9h - 28.5 89h - 44.5 a9h - 60.5 c9h - 76.5 e9h - 92.5 0ah 19.0 2ah 3.0 4ah - 13.0 6ah - 29.0 8ah - 45.0 aah - 61.0 cah - 77.0 eah - 93.0 0bh 18.5 2bh 2.5 4bh - 13.5 6bh - 29.5 8bh - 45.5 abh - 61.5 cbh - 77.5 ebh - 93.5 0ch 18.0 2ch 2.0 4ch - 14.0 6ch - 30.0 8ch - 46.0 ach - 62.0 cch - 78.0 ech - 94.0 0dh 17.5 2dh 1.5 4dh - 14.5 6dh - 30.5 8dh - 46.5 adh - 62.5 cdh - 78.5 edh - 94.5 0eh 17.0 2eh 1.0 4eh - 15.0 6eh - 31.0 8eh - 47.0 aeh - 63.0 ceh - 79.0 eeh - 95.0 0fh 16.5 2fh 0.5 4fh - 15.5 6fh - 31.5 8fh - 47.5 afh - 63.5 cfh - 79.5 efh - 95.5 10h 16.0 30h 0.0 50h - 16.0 70h - 32.0 90h - 48.0 b0h - 64.0 d0h - 80.0 f0h - 96.0 11h 15.5 31h - 0.5 51h - 16.5 71h - 32.5 91h - 48.5 b1h - 64.5 d1h - 80.5 f1h - 96.5 12h 15.0 32h - 1.0 52h - 17.0 72h - 33.0 92h - 49.0 b2h - 65.0 d2h - 81.0 f2h - 97.0 13h 14.5 33h - 1.5 53h - 17.5 73h - 33.5 93h - 49.5 b3h - 65.5 d3h - 81.5 f3h - 97.5 14h 14.0 34h - 2.0 54h - 18.0 74h - 34.0 94h - 50.0 b4h - 66.0 d4h - 82.0 f4h - 98.0 15h 13.5 35h - 2.5 55h - 18.5 75h - 34.5 95h - 50.5 b5h - 66.5 d5h - 82.5 f5h - 98.5 16h 13.0 36h - 3.0 56h - 19.0 76h - 35.0 96h - 51.0 b6h - 67.0 d6h - 83.0 f6h - 99.0 17h 12.5 37h - 3.5 57h - 19.5 77h - 35.5 97h - 51.5 b7h - 67.5 d7h - 83.5 f7h - 99.5 18h 12.0 38h - 4.0 58h - 20.0 78h - 36.0 98h - 52.0 b8h - 68.0 d8h - 84.0 f8h - 100.0 19h 11.5 39h - 4.5 59h - 20.5 79h - 36.5 99h - 52.5 b9h - 68.5 d9h - 84.5 f9h - 100.5 1ah 11.0 3ah - 5.0 5ah - 21.0 7ah - 37.0 9ah - 53.0 bah - 69.0 dah - 85.0 fah - 101.0 1bh 10.5 3bh - 5.5 5bh - 21.5 7bh - 37.5 9bh - 53.5 bbh - 69.5 dbh - 85.5 fbh - 101.5 1ch 10.0 3ch - .6.0 5ch - 22.0 7ch - 38.0 9ch - 54.0 bch - 70.0 dch - 86. 0 fch - 102.0 1dh 9.5 3dh - 6.5 5dh - 22.5 7dh - 38.5 9dh - 54.5 bdh - 70.5 ddh - 86.5 fdh - 102.5 1eh 9.0 3eh - 7.0 5eh - 23.0 7eh - 39.0 9eh - 55.0 beh - 71.0 deh - 87.0 feh - 103.0 1fh 8.5 3fh - 7.5 5fh - 23.5 7fh - 39.5 9fh - 55.5 bfh - 71.5 dfh - 87.5 ffh mute table 6 . adc digital volume sett ing list [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 90 - dac blocks 1. de - emphasis filter the ak775 5 has a digital de - emphasis filter (tc=50/15s) by iir filter, corresponding to 48khz sampling frequency. dem[1:0] bits control the de - emphasis filter . dem mode dem[1:0] sampling frequency (fs) 0 00 off (d e fault ) 1 01 48khz 2 10 44.1khz 3 11 32khz table 7 . de - emphasis control 2 . dac digital volume control the dacs of the ak7755 have channel independent volume control (256 levels, 0.5 step). the voldal/r[7:0] bits (cont18: d7 - d0 / cont19: d7 - d0), set the at tenuation level of each dac channel. dac lch voldal [7:0] dac rch voldar [7:0] attenuation level 00h 00h +12.0db 01h 01h +11.5db 02h 02h +11.0db : : : 17h 17h +0.5db 18h 18h 0.0db (default) 19h 19h - 0.5db : : : fdh fdh - 114.5db feh feh - 115.0db ffh ffh mute ( - ) pin is set to l, the vold a l /r [7:0] bits are initialized to 18h. [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 91 - table 10 . dac digital volume sett ing list 3. dac soft mute the dac block has a digital soft mute circuit. the soft mute operation is performed in the digital domain. the input signal is attenuated to - in dac digital volume level x att transition time from the current dac digital volume setting level by setting da mute bit (cont1a: d5) to 1. when the da mute bit is returned to 0, the mute is cancelled and the input attenuation gradually changes to dac digital volume setting level in dac digital volume level x att transition time. if the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to dac digital volume setting level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. the soft mute function works when the dac is in operation. since the dac block is in reset state, t here is a possibility that a click noise occurs by a reset and a reset release when cresetn bit (cont0f: d3) = 0 and pmdal/r bit (cont0e: d0/d1) = 0 . this click noise should be muted externally. t he a ttenuation value is initi alized by the pdn pin = l . figure 73 . dac soft mute operation code db code db code db code db code db code db code db code db 00h 12.0 20h - 4.0 40h - 20.0 60h - 36.0 80h - 52.0 a0h - 68.0 c0h - 84.0 e0h - 100.0 01h 11.5 21h - 4.5 41h - 20.5 61h - 36.5 81h - 52.5 a1h - 68.5 c1h - 84.5 e1h - 100. 5 02h 11.0 22h - 5.0 42h - 21.0 62h - 37.0 82h - 53.0 a2h - 69.0 c2h - 85.0 e2h - 101.0 03h 10.5 23h - 5.5 43h - 21.5 63h - 37.5 83h - 53.5 a3h - 69.5 c3h - 85.5 e3h - 101.5 04h 10.0 24h - .6.0 44h - 22.0 64h - 38.0 84h - 54.0 a4h - 70.0 c4h - 86.0 e4h - 102.0 05h 9.5 25h - 6.5 45h - 22.5 65h - 38.5 85h - 54.5 a5h - 70.5 c5h - 86.5 e5h - 102.5 06h 9.0 26h - 7.0 46h - 23.0 66h - 39.0 86h - 55.0 a6h - 71.0 c6h - 87.0 e6h - 103.0 07h 8.5 27h - 7.5 47h - 23.5 67h - 39.5 87h - 55.5 a7h - 71.5 c7h - 87.5 e7h - 103.5 08h 8.0 28h - 8.0 48h - 24.0 68h - 40.0 88h - 56.0 a8h - 72.0 c8h - 88.0 e8h - 104.0 09h 7.5 29h - 8.5 49h - 24.5 69h - 40.5 89h - 56.5 a9h - 72.5 c9h - 88.5 e9h - 104.5 0ah 7.0 2ah - 9.0 4ah - 25.0 6ah - 41.0 8ah - 57.0 aah - 73.0 cah - 89.0 eah - 105.0 0bh 6.5 2bh - 9.5 4bh - 25.5 6bh - 41.5 8bh - 57.5 abh - 73.5 cbh - 89.5 ebh - 105.5 0ch 6.0 2ch - 10.0 4ch - 26.0 6ch - 42.0 8ch - 58.0 ach - 74.0 cch - 90.0 ech - 106.0 0dh 5.5 2dh - 10.5 4dh - 26.5 6dh - 42.5 8dh - 58.5 adh - 74.5 cdh - 90.5 edh - 106.5 0eh 5.0 2eh - 11.0 4eh - 27.0 6eh - 43.0 8eh - 59.0 aeh - 75.0 ceh - 91.0 eeh - 107.0 0fh 4.5 2fh - 11.5 4fh - 27.5 6fh - 43.5 8fh - 59.5 afh - 75.5 cfh - 91.5 efh - 107.5 10h 4.0 30h - 12.0 50h - 28.0 70h - 44.0 90h - 60.0 b0h - 76.0 d0h - 92.0 f0h - 108.0 11h 3.5 31h - 12.5 51h - 28.5 71h - 44.5 91h - 60.5 b1h - 76.5 d1h - 92.5 f1h - 108.5 12h 3.0 32h - 13.0 52h - 29.0 72h - 45.0 92h - 61.0 b2h - 77.0 d2h - 93.0 f2h - 109.0 13h 2.5 33h - 13.5 53h - 29.5 73h - 45.5 93h - 61.5 b3h - 77.5 d3h - 93.5 f3h - 109.5 14h 2.0 34h - 14.0 54h - 30.0 74h - 46.0 94h - 62.0 b4h - 78.0 d4h - 94.0 f4h - 110.0 15h 1.5 35h - 14.5 5 5h - 30.5 75h - 46.5 95h - 62.5 b5h - 78.5 d5h - 94.5 f5h - 110.5 16h 1.0 36h - 15.0 56h - 31.0 76h - 47.0 96h - 63.0 b6h - 79.0 d6h - 95.0 f6h - 111.0 17h 0.5 37h - 15.5 57h - 31.5 77h - 47.5 97h - 63.5 b7h - 79.5 d7h - 95.5 f7h - 111.5 18h 0.0 38h - 16.0 58h - 32.0 78h - 48 .0 98h - 64.0 b8h - 80.0 d8h - 96.0 f8h - 112.0 19h - 0.5 39h - 16.5 59h - 32.5 79h - 48.5 99h - 64.5 b9h - 80.5 d9h - 96.5 f9h - 112.5 1ah - 1.0 3ah - 17.0 5ah - 33.0 7ah - 49.0 9ah - 65.0 bah - 81.0 dah - 97.0 fah - 113.0 1bh - 1.5 3bh - 17.5 5bh - 33.5 7bh - 49.5 9bh - 65.5 bbh - 81.5 dbh - 97.5 fbh - 113.5 1ch - 2.0 3ch - 18.0 5ch - 34.0 7ch - 50.0 9ch - 66.0 bch - 82.0 dch - 98.0 fch - 114.0 1dh - 2.5 3dh - 18.5 5dh - 34.5 7dh - 50.5 9dh - 66.5 bdh - 82.5 ddh - 98.5 fdh - 114.5 1eh - 3.0 3eh - 19.0 5eh - 35.0 7eh - 51.0 9eh - 67.0 beh - 83.0 deh - 99.0 feh - 115.0 1fh - 3.5 3fh - 19.5 5fh - 35.5 7fh - 51.5 9fh - 67.5 bfh - 83.5 dfh - 99.5 ffh mute damute register - db 0db attenuation output image ( setting +2 )/fs (max) ( setting +2 )/fs (max) gd gd soft mute operation [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 92 - analog output block the ak7755 can output an analog mixing signal of dac and line - in amplifier outputs from the out3 pin. ad conversio n is available by setting pmad 2l bit (cont0e: d5) to 1 even when the analog mixing output is on. figure 74 . analog output circuit 1. line output amplifier the ak7755 has a line output amplifier. the m aximum amplitude is 0.76 avdd ( 2.51[vpp] @avdd=3.3v) and load resistance is 10k ? (min) . lovol1/2/3[3:0] bits (cont14: d 3 - d0 / cont14: d 7 - d4 / cont13: d3 - d0) control the stereo line output volume. a pop noise occurs if the output gain is changed during oper ation. lovol 1,l2,l3 [3:0] attenuation lovol 1, l2, l3 [3:0] attenuation 0h mute (d efault ) 8h - 14db 1h - 28db 9h - 12db 2h - 26db ah - 10db 3h - 24db bh - 8db 4h - 22db ch - 6db 5h - 20db dh - 4db 6h - 18db eh - 2db 7h - 16db fh 0db table 11 . line ou t put volume 2. output 1 and output2 the out1 and out2 pins are connected to the l and r channels of the internal stereo dac, respectively. the relationship of each control bit and the out1 and out2 pins are shown below. the out1 and out2 pins o utput settings are controlled by pmlo1/2 bit (cont0e: d2/d3), pmdal/r bit (cont0e: d0 /d1 ) and lovol1/2[3:0] bits (cont014: d3 - d0/d7 - d4) . pmlo1 bit pmdal bit lovol1[3:0] bits out1 pin output 0 x x hi - z 1 0 x 1/2 x avdd 1 1 0h(mute) 1/2 x avdd 1 1 1h - f h dac lch output pmlo2 bit pmdar bit lovol2[3:0] bits out2 pin output 0 x x hi - z 1 0 x 1/2 x avdd 1 1 0h(mute) 1/2 x avdd 1 1 1h - fh dac rch output out1 pin lovol1[3:0] stereo dac lch stereo dac rch out2 pin lovol2[3:0] out3 pin lovol3[3:0] lo3sw1 (sw1) lo3sw2 (sw2) lo3sw3 (sw3) lign [3:0] lin pin mono adc m i x ak7755 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 93 - 3. out3 (analog mixer the ak7755 can output an analog mixing signal of dac and line - in amplifier outputs from the out3 pin by se tting lo3sw1 bit (cont09: d1) , lo3sw2 bit (cont09: d2) and lo3sw3 bit (cont09: d3) . the line - out amplifier is powered up by s etting pmlo3 bit = 1 . each switch is disconnected and t h e out3 pin outputs 1/2 avdd when lovol3[3:0] bits (cont13: d3 - d0) = 0h. l and r channel signals of the dac are input to the mixer by setting lo 3sw1 bit and lo3sw2 bit to 1 while the setting of l ovol3[3:0] bits is not 0h. l and r channel signals of the dac are not gained by the mixer block. the output signal of line - in amplifier is input to the mixer by setting lo3sw3 bit to 1 while the setting of lovol3[3:0] bits is not 0h. adjust the input v oltage and line - in amplifier gain (lign[3:0] bits (cont13: d7 - d4) ) to prevent the mixing output exceed s 0.67 avdd[vpp ] since the line - in amplifier output is gained +18db by the mixer block. the maximum amplitude of the line - out output is 0.76 avdd[v pp ] . voldal[7:0] bits (cont18: d7 - d0) , voldar[7:0] bits (cont19: d7 - d0) , lign[3:0] bits and lovol3[3:0] bits should be adjusted to not exceed this maximum level. pmlo3 lovol3[3:0] lo3sw1 lo3sw2 lo3sw3 sw1 sw2 sw3 0 x x x x off off off 1 0h(mute) x x x o ff off off 1 1h - fh 0 0 0 off off off 1 1h - fh 0 0 1 off off on 1 1h - fh 0 1 0 off on off 1 1h - fh 0 1 1 off on on 1 1h - fh 1 0 0 on off off 1 1h - fh 1 0 1 on off on 1 1h - fh 1 1 0 on on off 1 1h - fh 1 1 1 on on on table 12 . out3 pin output switching setting [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 94 - simple write error check ram and register data can be checked by cyclic redundancy check (crc). it re a l iz es a simple error check of a written data. 1. checked data 1 - 1. spi interface the serial input data of the ak7755 can be checked from a falling edge of the csn signal to rising edge of the csn signal. serial data d (x): input data from a falling edge to a rising edge of the csn. generating polynomial: g(x)=x 16 +x 12 +x 5 +1 ( default =0 ) r(x) is defined as the remainder when d(x) is divided by g(x ). 1 - 2. i 2 c interface the data after second byte: command code, address and data are checked. (acknowledge is not included in the checked data. therefore, if the command code, address and data are the same as when spi interface is used, the crc error result will also be the same.) the first byte which includes slave address is excluded. the first byte can be checked with acknowledge. serial data d(x): command code, address and data (expect slave address) generating polynom ial: g(x)=x 16 +x 12 +x 5 +1 (default =0 ) r (x) is defined as the remainder when d(x) is divided by g(x). 2. simple write error check sequence there are two ways to execute a simple write error check. 2 - 1. crc result reading (1) write serial data d (x) tha t need to be checked. (2) read crc result ( the remainder r (x)) by the command code 72h. (3) check the result by a microcomputer. (4) repeat (1) ~ (3) when checking another serial data. note 55 . the internal crc result is not reflect ed by the command code 2 - 2. checking by the sto pin (1) set control register crce bit to 1 . (2) write serial data d(x) that need to be checked. (3) write the remainder r(x) of d(x) ti registers by the command code f2h. (4) the sdo pin outputs h wh en the calculated remainder of d(x) divided by g(x) equals to the r(x) value. if not, the sto pin outputs l . (5) repeat (2) ~ (4) when checking another serial data. note 56 . t h e sto pin keeps l output until an appropriate remaind er r(x) is written to the registers. csn sclk si command code (8bit) address (16bit or 0bit) data (write) dont care (l/h) x (l/h) [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 95 - eeprom interface 1. data download the ak7755 has eeprom boot mode to read out necessary data from an external eeprom to the internal memory via i 2 c bus . a hands - free function is easily realized in the system using eeprom without extra overloads on the m icroprocessor. the external eeprom should be connected to the i 2 c interface of the ak775 5 (i2csel pin= h ). a spi interface type eeprom cannot be connected. write data as shown in 2. program map to the eeprom. control registers can shift the write comm and code and data in 2 byte unit. however, the data location from the pram write comm and code ( 0034h ) to ofreg address 31lsb (689 c h) is fixed. set 1010000 to i 2 c slave address of the eeprom when 256k bit, and set 101000+a16 when 1m bit . t h e a k7755 s tarts downloading the data from the eeprom when setting the exteep pin to h or dls bit (cont0d : d0) to 1 while the exteep pin = l after inputting a 12.288mhz clock to the xti pin or connecting a 12.288mhz crystal oscillator to the xti pin and the xto pin . the eest (sdout1) pin goes to h while downloading data and the ak7755 becomes an i 2 c master . do not write/read to the other devices that are connected to the same i 2 c bus during downloading. the eest pin returns to l after downloading data and th e ak7755 will be in i 2 c slave mode. interfacing to a microco ntroller becomes available when the eest pin = l . when accessing the ak7755 after downloading data by crc function, set crce bit (cont10: d6) to 0 before access the ak7755. the eeprom downlo ad period is 0. 8 s (max). set the exteep pin h l h or dls bit (cont0d, d0) 1 0 1 to start a data downloading again . however, data downloading cannnot be executed by dls bit when selecting memory mat (i2csel pin = matsel pin = h ). figure 75 . eeprom connection ( left : eeprom only , right : cpu and eeprom ) eeprom scl sda sda scl pdn i2csel= h exteep p / eeprom interf ace control eest ( sdout1 ) sto eeprom scl sda p / eeprom interface sda eest ( sdout1 ) scl pdn i2csel = h exteep p scl sda sto gpi 2 gpi 1 control [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 96 - 2. program map eeprom a ddress data note 0000h c0h cont 0 0 w rite c o mmand code 0001h data cont 0 0 data 0002h c 1 h cont 0 1 w rite c o mmand code 0003h data cont 0 1 data 0004h c 2 h cont 0 2 w rite c o mmand code 0005h data cont 0 2 data 0006h c 3 h cont 0 3 w rite c o mmand code 0007h data cont 0 3 data 0008h c 4 h cont 0 4 w rite c o mmand code 0009h data cont 0 4 data 000ah c 5 h cont 0 5 w rite c o mmand code 000bh data cont 0 5 data 000ch c 6 h cont 0 6 w rite c o mma nd code 000dh data cont 0 6 data 000eh c 7 h cont 0 7 w rite c o mmand code 000fh data cont 0 7 data 0010h c 8 h cont 0 8 w rite c o mmand code 0011h data cont 0 8 data 0012h c 9 h cont 0 9 w rite c o mmand code 0013h data cont 0 9 data 0014h c a h cont 0a w rite c o mmand code 001 5h data cont 0a data 0016h c c h cont 0c w rite c o mmand code 0017h data cont 0c data 0018h d 0h cont 1 0 w rite c o mmand code 0019h data cont 1 0 data 001ah d1 h cont 11 w rite c o mmand code 001bh data cont 11 data 001ch d2 h cont 12 w rite c o mmand code 001dh data cont 1 2 data 001eh d3 h cont 1 3 w rite c o mmand code 001fh data cont 1 3 data 00 2 0h d4 h cont 1 4 w rite c o mmand code 00 2 1h data cont 1 4 data 00 2 2h d5 h cont 1 5 w rite c o mmand code 00 2 3h data cont 1 5 data 0024h d6 h cont 1 6 w rite c o mmand code 0025h data cont 1 6 data 0026 h d7 h cont 1 7 w rite c o mmand code 0027h data cont 1 7 data 0028h d8 h cont 1 8 w rite c o mmand code 0029h data cont 1 8 data 00 2 ah d9 h cont 1 9 w rite c o mmand code 00 2 bh data cont 1 9 data 00 2 ch da h cont 1a w rite c o mmand code 002dh data cont 1a data 002eh 00h dummy da ta 0 0 ( note 58 ) 002fh 00h dummy data 0 1 00 3 0h 00h dummy data 1 0 00 3 1h 00h dummy data 1 1 0032h 00 h dummy data2 0 ( note 57 ) 0033h 00h dummy data2 1 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 97 - 0034h b8h p ram write command code 0035h 00h pram address msb side 0036h 00h pram address lsb side 0037h pram0 data39 - 32 pram address 0 msb 8 - bit data 00 38 h pram0 data31 - 24 pram address 0 msb - 1 8 - bit data 00 39 h pram0 data23 - 16 pram address 0 msb - 2 8 - bit data 00 3a h pram0:data15 - 8 pram address 0 msb - 3 8 - bit data 003bh pram0 data7 - 0 pram address 0 lsb 8 - bit data 003ch pram1 data39 - 32 pram address 1 msb 8 - bit data 003dh pram 1 data31 - 24 pram address1 msb - 1 8 - bit data 003eh pram 1 data23 - 16 pram address1 msb - 2 8 - bit d ata 003fh pram 1 :data15 - 8 pram address1 msb - 3 8 - bit data 0040h pram 1 data7 - 0 pram address1 lsb 8 - bit data 0041h pram 2 data39 - 32 pram address2 msb - 1 8 - bit data ? ? ? ? ? ? 5031 h pram 4094 data7 - 0 pram address4094 lsb 8 - bit data 5032 h pram 4095 data39 - 32 pram address4095 msb 8 - bit data 5033 h pram 4095 data31 - 24 pram address4095 msb - 1 8 - bit data 5034 h pram 4095 data23 - 16 pram address4095 msb - 2 8 - bit data 5035 h pram 4095 data15 - 8 pram address 4095 msb - 3 8 - bit data 5036 h pram 4095 data7 - 0 pram address4095 lsb 8 - bit data 5037 h b4h cram write command code 5038 h 00h cram address msb side 5039 h 00h cram address lsb side 503a h cram0 data 23 - 16 cram address 0 msb 8 - bit data 503b h cram0 data15 - 8 cram address 0 msb - 1 8 - bit data 503ch cram0 data7 - 0 cram ad dress 0 lsb 8 - bit data 503dh cram1 data 23 - 16 cram address 1 msb 8 - bit data ? ? ? ? ? ? 6836h cram2046 data7 - 0 cram address 2046 lsb 8 - bit data 6837h cram2047 data 23 - 16 cram address 2047 msb 8 - bit data 6838h cram2047 data15 - 8 cram address 2047 m sb - 1 8 - bit data 6839h cram2047 data7 - 0 cram address 2047 lsb 8 - bit data 683a h b 2 h ofreg write command code 683b h 00h ofreg address msb side 683c h 00h ofreg address lsb side 683d h ofreg 0 data 23 - 16 ofreg address 0 msb 8 - bit data 683e h ofreg0 data1 5 - 8 ofreg address 0 msb - 1 8 - bit data 683f h ofreg0 data7 - 0 ofreg address 0 lsb 8 - bit data 6840h ofreg1 data 23 - 16 ofreg address 1 msb 8 - bit data ? ? ? ? ? ? 6899 h ofreg30 data7 - 0 ofreg address30 lsb 8 - bit data 689ah ofreg31 data 23 - 16 ofreg a ddress 31 msb 8 - bit data 689b h ofreg31 data15 - 8 ofreg address 31 msb - 1 8 - bit data 689c h ofreg31 data7 - 0 ofreg address 31 lsb 8 - bit data 689dh c d h cont 0d w rite command code 689eh 40h cont 0d data 689fh e6h cont 26 w rite command code 68a0h 01h con t 26 data 68a1h ea h cont 2a w rite command code 68a2h 8 0h cont 2a data 68a3h c e h cont 0e write command code 68a4h data cont 0e data 68a5h c f h cont 0f write command code 68a6h data cont 0f data 68a7h 00h dummy data 0 _0 68a8h 00h dummy data 0 _1 68a9h 00h dumm y data 1 _0 68aah 00h dummy data 1 _1 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 98 - 68abh 00h dummy data 2 _0 68ach 00h dummy data 2 _1 68adh 00h dummy data 3 _0 68aeh 00h dummy data 3 _1 68afh 00h dummy data 4 _0 68b0h 00h dummy data 4 _1 68b1h 00h dummy data 5 _0 68b2h 00h dummy data 5 _1 68b3h 00h dummy data 6 _0 68b4h 00h dummy data 6 _1 68b5 h f2h crc write command code 68b6 h crc data15 - 8 crc msb 8 - bit data 68b7h crc data7 - 0 crc lsb 8 - bit data 68b8h 00h reserve ? ? ? ? ? ? 7fffh 00h reserve note 57 . dspresetn bit (cont0f: d2) must be 0 when downloading a dsp program. especially this setting is necessary when changing the dsp program during operation by selecting eeprom mat. note 58 . a write command for arbitrary con trol register can be written to dummy dat a *_0 , and write register setting for the control register to dummy data*_1 in the table above. data transffer from eeprom can be confirmed by writing r(x) (16 - bit) data to crcdata (addr: 787ch, 787dh) which is the remainder of serial data d(x) from addr es 0000h to 68b7 h devided by a generating polynominal; g(x)=x 16 +x 12 +x 5 +1 (initial value= 0). 3. eeprom automatic re - downloading when a programmed wdt or crc error is detected, automatic re - downloading of the eeprom data is ava i lable up to 4 times by set ting the expeep pin = h . when an error occurs after re - down loading more than 4 times, l level is output on the sto pin and the device stops. the device status can be checked by reading sto bit (cont0d: d7). the crc function is enabled by setting crce b it ( cont10: d6 ) to 1 . t he default setting of crce bit is 0 (disabled). this setting is initialized (error count: 0) by the pd n pin = l . it is not initialized by a c lock r eset. 4. eeprom mat select the pin number 20 becomes the matsel pin that ena bles eeprom program mat selecting when the exteep pin = h . connect a 256k - bit eeprom and bring the matsel pin = l when not selecting the eeprom mat. connect a 1m - bit eeprom and bring the matsel pin = h when selecting the eeprom mat. in this case, th e pin numb er 1 4 (mat1) and 1 5 ( mat0) are address pins of the mat select. single program is stored in every 256k bits as a program map. the eeprom can store four programs in total. the mat1 and mat0 pins select a program to download to the ak7755. out3e bi t (cont0a, d2) and out2e bit (cont0a, d1) must not set to 1 when selecting an eeprom mat (matsel pin = h ). program no. mat1 ( 14 pin) mat0 (1 5 pin) eeprom storing beginning address i 2 c 1st byte 1 0 0 17 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 99 - digital microphone interface 1. digital mic connection f our digital microphones can be connected to the ak7755 at the maximum . when dm ic 1 (cont1e: d7) or dmic2 (cont1e: d4) bit is set to 1, the #34 pin become s dmdat 1 (di gital microphone data input) , t he #33 pin becomes dmclk 1 (digital microphone clock supply) pins , the #32 pin becomes dmdat2 pin and the #31 pin becomes dmclk2 pin . the dmclk 1/2 clock is an input to a digital microphone from the ak 7755 . the digital microphone outputs 1bit data, which is generated by ? ? modulator using dmclk 1/2 clock , to the dmdat 1/2 pin. d mic 1/2 bit control s power up/down of the digital block (decimation filter and digital filter). dclke 1/2 b it (cont1e: d5/d2) controls o n/off of the output clock from the dmclk 1/2 pin. when the ak 7755 is powered down (pdn pin= l ), the dmclk 1/2 and dmdat 1/2 pins become floating state. pull - down resistors must be connected to dmclk and dmdat pins externally to avoid this floating state. figure 76 sho ws a stereo 4ch connection example. figure 76 . connection example for 4ch stereo digital microphone amp ? ? ?? modulator dmdat 1 dmclk 1 (64fs) decimation filter digital filter sd outad vdd ak775 5 a vdd amp ? ? ?? modulator vdd lch rch d mic1 or dmic2 bit = 1 dmic 1 bit = 1 amp ? ? ?? modulator vdd amp ? ? ?? modulator vdd lch rch dmdat 2 decimation filte r digital filter sdoutad 2 dmic 2 bit = 1 100k ? d mic1 or dmic2 bit = 1 dmclk2(64fs) 100k ? 100k ? 100k ? [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 100 - 2. interface the input data channel of the dmdat 1/2 pin is set by dclkp 1/2 bit (cont1e: d6/d3) . when dclkp 1/2 bit = 1, l channel data is input to the decimation filter if the dmclk 1/2 pin = h, and r channel data is input if the dmclk 1/2 = l. when dclkp 1/2 bit = 0, r channel data is input to the decimation filter while dmclk 1/2 pin = h, and l chan nel data is input while dmclk 1/2 pin = l. the dmclk 1/2 pin only supports 64fs. it outputs l when dclke 1/2 bit = 0, and outputs 64fs clock when dclke 1/2 bit = 1. the output data through the decimation and digital filters is 24bit full scale when th e 1bit data density is 0%~100%. dclkp 1 bit dmclk 1 pin = h dmclk 1 pin = l 0 rch lch (default) 1 lch rch dclkp 2 bit dmclk 2 pin = h dmclk 2 pin = l 0 rch lch (default) 1 lch rch table 13 . data in put /output timing wit h digital mic figure 77 . data input/output timing with digital mic (dclkp 1/2 bit = 1 ) figure 78 . data input/output timing with digital mic (dclkp 1 /2 bit = 0 ) digital mixer adc output (sdatad) , adc 2 output (sdatad2) and dsp - dout4 data can be mixed into a signle serial data by a mixer circuit. selmix[2:0] bits (cont09: d0, cont08: d1, d0 ) c ontrol mixing setting. delay time of the mixer circuit is 4ts (4/fs). sel mix mode sel mix [ 2 :0] mixout lch mixout rch 0 00 0 sdoutad lch sdoutad rch (default) 1 0 01 sdoutad lch/2 + sdoutad2 lch/2 sdoutad rch 2 0 10 sdoutad lch sdoutad lch/2 + sdoutad2 lch/2 3 0 11 sdoutad2 lch sdoutad2 r ch 4 100 dsp - dout 4 lch sdoutad2 rch 5 101 sdoutad2 lch dsp - dout4 rch 6 110 dsp - dout4 lch sdoutad rch 7 111 sdoutad lch dsp - dout4 rch table 14 . digital mixer output setting dmclk 1/2 (64fs) dmdat 1/2 (lch) valid data valid data valid data valid data dmdat 1/2 (rch) valid data valid data valid data valid data dmclk 1/2 (64fs) dmdat 1/2 (lch) valid data valid data valid data valid data dmdat 1/2 (rch) valid data valid data valid data valid data [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 101 - 10. recommended external circuits connection diagram 1. i2csel pin = l , ldoe pin = l figure 79 . serial interface connection with external power s u pply 2. i2csel pin = l , ldoe pin = h figure 80 . serial interface connection with internal ldo so clko bick xto xti rd c l=22pf/15pf c l= 22 pf /15pf 9 8 1 1 2 2 csn si 1 9 20 1 7 up 2, 30 1 2 digital io 1.8 3.3 v pdn t vdd reset control ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 clock i 2csel 3 l s clk & sdout1 sdout2 sdout3 s di n1 1 6 1 5 1 4 5 1 8 6 sto/rdy 10 sdin2 4 2 1 , 29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 digital core 1.2v d vdd 10 ? 0.1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/ inn2 31 2 7 out2 2 6 out1 2 8 out3 dvss 13, 2 5 ldoe 2 3 l 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? so clko bick xto xti rd c l=22pf/15pf c l= 22 pf /15pf 9 8 1 1 2 2 csn si 1 9 20 1 7 up 2, 30 1 2 digital io 1.8 3.3 v pdn t vdd reset control ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 clock i 2csel 3 l s clk & sdout1 sdout2 sdout3 s di n1 1 6 1 5 1 4 5 1 8 6 sto/rdy 10 sdin2 4 2 1 , 29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 avdrv 1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn2 31 2 7 out2 2 6 ou t1 2 8 out3 dvss 13, 25 ldoe 2 3 h 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 102 - 3. i2csel pin = h , exteep pin = l , ldoe pin = l figure 81 . i 2 c interface connection with external power s u pply 4. i2csel pin = h , exteep pin = l , ldoe pin = h figure 82 . i 2 c interface connection with internal ldo s da clko bick xto xti rd c l=22pf/15pf cl=22pf/15pf 9 8 1 1 2 2 scl exteep 1 9 1 8 1 7 up 2 , 30 1 2 digital io 1.8 3.3 v pdn t vdd reset control ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 c lock i2csel 3 h cad & sdout1 sdout2 sdout3 s di n1 1 6 1 5 1 4 5 20 6 sto/rdy 10 sdin2 4 2 1 ,29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 digital core 1.2v d vdd 10 ? 0.1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn2 31 2 7 out2 2 6 out1 2 8 out3 dvss 13, 2 5 ldoe 2 3 l l 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? s da clko bick xto xti rd c l=22pf/15pf cl=22pf/15pf 9 8 1 1 scl exteep 1 9 1 8 1 7 up 2 , 30 1 2 digital io 1.8 3.3 v t vdd ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 c lock i2csel 3 h cad & sdout1 sdout2 sdout3 s di n1 1 6 1 5 1 4 5 20 6 sto/rdy 10 sdin2 4 2 1 ,29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 avdrv 1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn2 31 2 7 out2 2 6 out1 2 8 out3 dvss 13, 2 5 ldoe 2 3 h l 2 2 pdn reset control 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 103 - 5. i2csel pin = h , exteep pin = h , matsel pin = l , ldoe pin = l figure 83 . i 2 c interface connection with external power s u pply and eeprom 6. i2csel pin = h , exteep pin = h , matsel pin = l , ldoe pin = h figure 84 . i 2 c interface connection with i nternal ldo and eeprom s da clko bick xto xti rd c l=22pf/15pf cl=22pf/15pf 9 8 1 1 scl exteep 1 9 1 8 1 7 up 2 , 30 1 2 digital io 1.8 3.3 v t vdd ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 c lock i2csel 3 h & sdout1 sdout2 sdout3 s di n1 1 6 1 5 1 4 5 6 sto/rdy 10 sdin2 4 2 1 ,29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 digital core 1.2v d vdd 10 ? 0.1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn 2 31 2 7 out2 2 6 out1 2 8 out3 dvss 13, 2 5 ldoe 2 3 l eeprom 256kbit matsel 20 h l 2 2 pdn reset control 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? s da clko bick xto xti rd c l=22pf/15pf cl=22pf/15pf 9 8 1 1 scl 1 8 1 7 up 2 , 30 1 2 digital io 1.8 3.3 v t vdd ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 clock i2csel 3 h & sdout1 sdout2 sdout3 s di n1 1 6 1 5 1 4 5 6 sto/rdy 10 sdin2 4 2 1 ,29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 avdrv 1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn2 31 2 7 out2 2 6 out1 2 8 out3 d vss 13, 2 5 ldoe 2 3 h eeprom 256kbit exteep 1 9 matsel 20 h l 2 2 pdn reset control 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 104 - 7. i2csel pin = h , exteep pin = h , matsel pin = h , ldoe pin = l figure 85 . i 2 c interface connection with external power s u pply and eeprom (mat select on) 8. i2csel pin = h , exteep pin = h , matsel pin = h , ldoe pin = h figure 86 . i 2 c interface connection with internal ldo and eeprom (mat select on) s da clko bick xto xti rd c l=22pf/15pf cl=22pf/15pf 9 8 1 1 scl exteep 1 9 1 8 1 7 up 2 , 30 1 2 digital io 1.8 3.3 v t vdd ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 c lock i2csel 3 h & sdout1 s di n1 1 6 5 6 sto/rdy 10 sdin2 4 2 1 ,29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 digital core 1.2v d vdd 10 ? 0.1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn2 31 2 7 out2 2 6 out 1 2 8 out3 dvss 13, 2 5 ldoe 2 3 l eeprom 1m bit matsel 20 h h mat0 1 5 mat1 1 4 2 2 pdn reset control 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? s da clko bick xto xti rd c l=22pf/15pf cl=22pf/15pf 9 8 1 1 scl 1 8 1 7 up 2 , 30 1 2 digital io 1.8 3.3 v t vdd ak77 55 avss 10 ? audio i/f 0.1 ? lr ck 7 clock i2csel 3 h & sdout1 s di n1 1 6 5 6 sto/rdy 10 sdin2 4 2 1 ,29,36 analog +3.3 v avdd 10 ? 0.1 ? 2 4 avdrv 1 ? vcom 1 2.2 ? in2/inn1 in1/inp1 lin 33 34 3 5 in3/inp2 32 in4/inn2 31 2 7 out2 2 6 out1 2 8 out3 dvss 13, 2 5 ldoe 2 3 h eeprom 1m bit exteep 1 9 matsel 20 h h mat0 1 5 mat1 14 2 2 pdn reset control 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 ? [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 105 - peripheral circuit 1. ground a vss and dvss must be connected to the same analog ground plane. decoupling capacitors, particularly small capacity capacitors, should be connected as close as possible to the ak77 55 . 2. reference voltage the avdd voltage controls analog signal range. vcom is a common voltage of this c hip and the vcom pin outputs a vdd/2. a 2.2f ceramic capacitor connected between the vcom and a vss pins eliminates the effects of high frequency noise. the ceramic capacitor should be connected as close as possible to the vcom pin. the vcom pin must not be connected to external circuits. digital signal lines, especially clock signal line should be kept away as far as possible from th e vcom pin in order to avoid unwanted coupling into the ak77 55 . 3. analog input analog input signals are applied to the modul ator through the input pin of each channel. input voltage is fs = (avdd - avss ) x 2. 2 /3.3 for differential pin and fs = (avdd - avss ) x 2. 2 /3.3 for single - end pin. when avdd = 3.3v and a vss=0.0v , t he differential input range is 2. 2 0vpp (typ) and it is 2.20v pp (typ) for single - end ed input . the digital output code format is 2's complements. dc offset can be cancelled by an internal hpf. the ak 7755 samples the analog inputs in 3.072mhz at fs = 48khz . the digital filter re moves noise in the range from 30khz to 3.042mhz. the ak 7755 includes an anti - aliasing filter (rc filt er) to attenuate a noise around the range from 3 .0 42mhz to 3.072mhz witch is not removed by the hpf . an external low pass filter is not necessary since most of a udio signals do not have large n oise in the band around 3.072mhz. however, it is recommended to connect a low pass filter before the adc when a signal with large out - of - band noises is input. the analog source voltage to the ak 7755 is +3.3v ( typ ) . voltage of a vdd + 0.3v or more, voltage of a vss C 0.3v or less, and current of 10ma or more must not be applied to a nalog input pins. excessive current will damage the internal protection circuit and will cause latch - up, damaging the ic. i f the external analog circuit voltage is 15v, the analog input pins must be protected from signals which are in absolute maximum rating level or more. figure 87 . input buffer circuit example ( differential input ) i np* 10k 10k 10k 10k i nn* signal + - - + 2 .2 0vpp 2 .2 0vpp 1 1 + + 22 + 68p 68p [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 106 - 4 . analog output the analog line - outputs are single - ended. the output signal range is 0.76 avdd vpp (typ.) centered around vcom voltage . the input code format is in 2s complement . the output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal voltage at 000000h is vcom . the vcom voltage is avdd/ 2 (typ) . the internal switched - capacitor filter (scf) and continuous - time filter (ctf) attenuate the noise generated by the delta - sigma modulator beyond the audio passband. 5 . connection to digit al circuit to minimize the noise from digital circuits, the digital output of the ak77 55 must be connected to cmos or low voltage logic ics such as 74hc and 74ac for cmos and 74lv, 74lv - a, 74alvc and 74avc for low voltage logic ics. 6 . cristal oscillator the resistor and capacitor values for the oscillator rc circuit are shown blow. tvdd = 3.0 - 3.6 v ckm mode xtal oscillator r1_max c0_max xti, xto pin connection capacity 0 12.288mhz 120 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 107 - 11 . p ackage outline dimensions package & lead frame material packag e molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 108 - marking 1) pin #1 indication 2) date code: xxxx( 4 digits) 3) marking code: 7755 en 1) pin # 1 indication 2) date code: xxxx( 4 digits) 3) marking code: 7755 vn akm 775 5 en xxxx 1 3 6 akm 775 5 v n xxxx 1 3 6 [ ak 7 755 ] 014006643 - e - 00 2014/ 10 - 109 - 1 2 . revision history date (y/m/d) revision reason page contents 14 / 1 0 / 2 0 00 first edition important notice 0. asahi kasei microdevices corporation (akm) reserves the right to make changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to c urrent status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information contained in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , in cluding but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control co mbustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works conti nually to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a m alfunction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this do cument for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roduct s or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as th e rohs compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability fo r damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm . |
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